mirror of
https://github.com/brandonlw/Psychson.git
synced 2026-10-16 21:12:54 +08:00
Brandon Wilson
288 lines
7.8 KiB
C
288 lines
7.8 KiB
C
#ifndef DEFS_H
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#define DEFS_H
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#define MSB(word) (BYTE)(((WORD)(word) >> 8) & 0xff)
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#define LSB(word) (BYTE)((WORD)(word) & 0xff)
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#define XVAL(addr) (*( __xdata volatile unsigned char *)(addr))
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#define IVAL(addr) (*( __idata volatile unsigned char *)(addr))
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typedef unsigned char BYTE;
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typedef unsigned short WORD;
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typedef unsigned long DWORD;
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typedef __bit BOOL;
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typedef __bit bit;
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#define TRUE 1
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#define FALSE 0
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#define USB_VECT 0
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#define TMR0_VECT 1
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#define EP_VECT 2
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#define TMR1_VECT 3
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#define COM0_VECT 4
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#define bmAttach 0x80
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#define bmSpeed 7
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#define bmSuperSpeed 4
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#define bmHighSpeed 0
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#define bmFullSpeed 1
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#define bmSpeedChange 0x80
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#define bmEP2IRQ 2
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#define bmEP0ACK 1
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#define bmEP0NAK 2
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#define bmEP0IN 4
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#define bmEP0STALL 8
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#define bmSUDAV 0x80
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#define bmSTALL 2
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#define bmNandReady 1
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#define bmNandDma0 0
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#define bmNandDma1 0x80
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#define bmNandDmaRead 0
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#define bmNandDmaWrite 0x40
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#define bmDmaCmd 7
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#define bmDmaCopy 2
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#define bmDmaFill 4
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#define bmDmaWidth8 0
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#define bmDmaWidth16 0x40
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#define bmDmaWidth32 0x80
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#define bmPRAM 1
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// ------------------------------------------------------------------------------------------------
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// * SFRs
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// * ------------------------------------------------------------------------------------------------
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// BYTE Register
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__sfr __at (0x80) P0 ;
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__sfr __at (0x90) P1 ;
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__sfr __at (0xA0) P2 ;
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__sfr __at (0xB0) P3 ;
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__sfr __at (0xD0) PSW ;
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__sfr __at (0xE0) ACC ;
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__sfr __at (0xF0) B ;
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__sfr __at (0x81) SP ;
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__sfr __at (0x82) DPL ;
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__sfr __at (0x83) DPH ;
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__sfr __at (0x87) PCON;
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__sfr __at (0x88) TCON;
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__sfr __at (0x89) TMOD;
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__sfr __at (0x8A) TL0 ;
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__sfr __at (0x8B) TL1 ;
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__sfr __at (0x8C) TH0 ;
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__sfr __at (0x8D) TH1 ;
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__sfr __at (0xA8) IE ;
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__sfr __at (0xB8) IP ;
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__sfr __at (0x98) SCON;
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__sfr __at (0x99) SBUF;
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/* BIT Register */
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/* PSW */
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__sbit __at (0xD7) CY ;
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__sbit __at (0xD6) AC ;
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__sbit __at (0xD5) F0 ;
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__sbit __at (0xD4) RS1 ;
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__sbit __at (0xD3) RS0 ;
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__sbit __at (0xD2) OV ;
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__sbit __at (0xD0) P ;
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/* TCON */
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__sbit __at (0x8F) TF1 ;
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__sbit __at (0x8E) TR1 ;
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__sbit __at (0x8D) TF0 ;
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__sbit __at (0x8C) TR0 ;
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__sbit __at (0x8B) IE1 ;
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__sbit __at (0x8A) IT1 ;
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__sbit __at (0x89) IE0 ;
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__sbit __at (0x88) IT0 ;
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/* IE */
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__sbit __at (0xAF) EA ;
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__sbit __at (0xAC) ES ;
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__sbit __at (0xAB) ET1 ;
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__sbit __at (0xAA) EX1 ;
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__sbit __at (0xA9) ET0 ;
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__sbit __at (0xA8) EX0 ;
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/* IP */
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__sbit __at (0xBC) PS ;
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__sbit __at (0xBB) PT1 ;
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__sbit __at (0xBA) PX1 ;
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__sbit __at (0xB9) PT0 ;
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__sbit __at (0xB8) PX0 ;
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/* P3 */
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__sbit __at (0xB7) RD ;
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__sbit __at (0xB6) WR ;
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__sbit __at (0xB5) T1 ;
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__sbit __at (0xB4) T0 ;
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__sbit __at (0xB3) INT1;
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__sbit __at (0xB2) INT0;
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__sbit __at (0xB1) TXD ;
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__sbit __at (0xB0) RXD ;
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/* SCON */
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__sbit __at (0x9F) SM0 ;
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__sbit __at (0x9E) SM1 ;
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__sbit __at (0x9D) SM2 ;
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__sbit __at (0x9C) REN ;
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__sbit __at (0x9B) TB8 ;
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__sbit __at (0x9A) RB8 ;
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__sbit __at (0x99) TI ;
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__sbit __at (0x98) RI ;
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// ------------------------------------------------------------------------------------------------
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// Xdata F000-F3FF USB Registers
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// ------------------------------------------------------------------------------------------------
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// some banking registers switching
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// value: 0-7, default: 0
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__xdata __at 0xF000 volatile BYTE REGBANK;
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__xdata __at 0xF008 volatile BYTE USBCTL;
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__xdata __at 0xF009 volatile BYTE USBSTAT;
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__xdata __at 0xF027 volatile BYTE USBIRQ;
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__xdata __at 0xF020 volatile BYTE EPIRQ;
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__xdata __at 0xF030 volatile BYTE EPIE;
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__xdata __at 0xF048 volatile BYTE EP0CS;
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__xdata __at 0xF0B8 volatile BYTE SETUPDAT[8];
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typedef struct
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{
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BYTE r0,r1,r2,r3,r4;
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BYTE ptr_l, ptr_m, ptr_h; //buffer ptr = buf_pa>>8
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BYTE r8,r9;
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BYTE ofs; // buffer offset, data addr will be ptr<<8 + ofs*0x200
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BYTE rB;
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BYTE len_l, len_m, len_h; //C,D,E
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BYTE rF,r10,r11,r12;
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BYTE cs; //13
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BYTE r14,r15,r16,r17,r18,r19;
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BYTE fifo_count;
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BYTE r1B;
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BYTE fifo; //1C
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} EPREGS;
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__xdata __at 0xF1C0 volatile EPREGS EP0;
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__xdata __at 0xF200 volatile EPREGS EP1;
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__xdata __at 0xF240 volatile EPREGS EP2;
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__xdata __at 0xF280 volatile EPREGS EP3;
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__xdata __at 0xF2C0 volatile EPREGS EP4;
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typedef struct
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{
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BYTE raw_cmd;
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BYTE u1[3];
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BYTE raw_addr;
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BYTE u5[3];
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BYTE raw_data;
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BYTE r9;
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BYTE uA[2];
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BYTE rC;
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BYTE uD[3];
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BYTE r10;
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BYTE u11[7];
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BYTE r18;
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BYTE u19[5];
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BYTE status; // .0 - R/nB
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BYTE u1F[0x19];
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BYTE r38, r39, r3A;
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BYTE u3B;
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BYTE r3C, r3D;
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BYTE u3E[2];
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BYTE r40;
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BYTE dma_size; // DMA size in KB
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BYTE r42;
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BYTE dma_mode; // DMA modes
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BYTE u44[3];
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BYTE r47;
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BYTE u48[0x14];
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BYTE r5C; // nand command
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// DMA command. |=1 to go, wait until .0 cleared
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BYTE dma_cmd;
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BYTE u61[0x0B];
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BYTE dma1_page; // DMA1 start page. Autoincrements
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BYTE u6D[3];
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BYTE dma0_page; // DMA0 start page. Autoincrements
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BYTE u71[3];
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// DMA1 PA. This pseudo reg sets dma1_page actually. RAZ
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BYTE dma1_ptr0, dma1_ptr1, dma1_ptr2, dma1_ptr3;
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// DMA0 PA. This pseudo reg sets w_dma_page actually. RAZ
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BYTE dma0_ptr0, dma0_ptr1, dma0_ptr2, dma0_ptr3;
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BYTE u7C[4];
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BYTE r80;
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BYTE u81[0x1B];
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BYTE page_size_l, page_size_h; // 9C full page size with spare
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BYTE r9E, r9F;
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BYTE uA0[0x4C];
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BYTE rEC;
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BYTE uED[0x13];
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} NANDREGS;
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__xdata __at 0xF400 volatile NANDREGS NFC0;
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__xdata __at 0xF500 volatile NANDREGS NFC1;
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__xdata __at 0xF608 volatile BYTE NANDCSOUT;
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__xdata __at 0xF618 volatile BYTE NANDCSDIR;
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//F638, F639 - scrambler control
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//F638 | 18 & 7F - turn off descrambler
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__xdata __at 0xF700 volatile NANDREGS NFCX;
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// DMA copy source / fill destination physical address
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__xdata __at 0xF900 volatile BYTE DMASRCL;
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__xdata __at 0xF901 volatile BYTE DMASRCM;
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__xdata __at 0xF902 volatile BYTE DMASRCH;
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// DMA copy destination physical address
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__xdata __at 0xF904 volatile BYTE DMADSTL;
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__xdata __at 0xF905 volatile BYTE DMADSTM;
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__xdata __at 0xF906 volatile BYTE DMADSTH;
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// DMA copy size in bytes (always in bytes, regardless of cmd width)
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__xdata __at 0xF908 volatile BYTE DMASIZEL;
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__xdata __at 0xF909 volatile BYTE DMASIZEM;
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__xdata __at 0xF90A volatile BYTE DMASIZEH;
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// DMA fill value
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__xdata __at 0xF90C volatile BYTE DMAFILL0;
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__xdata __at 0xF90D volatile BYTE DMAFILL1;
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__xdata __at 0xF90E volatile BYTE DMAFILL2;
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__xdata __at 0xF90F volatile BYTE DMAFILL3;
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// DMA command
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__xdata __at 0xF930 volatile BYTE DMACMD;
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// ------------------------------------------------------------------------------------------------
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// Xdata FA00-FAFF SYSTEM Registers
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// ------------------------------------------------------------------------------------------------
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__xdata __at 0xFA14 volatile BYTE GPIO0DIR;
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__xdata __at 0xFA15 volatile BYTE GPIO0OUT;
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__xdata __at 0xFA38 volatile BYTE WARMSTATUS;
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// XDATA banking
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// XDATA consists of 3 mapped areas: BANK0,1,2
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// BANK0 start is fixed at 0000, BANK1,2 starts at variable addresses
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// in case of overlapped addresses a bank with higher number has higher priority
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// xdata BANK0 mapping registers
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// maps XDATA VA 0000 to PA=BANK0PAH:L<<9, size - up to BANK1/2
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__xdata __at 0xFA40 volatile BYTE BANK0PAL;
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__xdata __at 0xFA41 volatile BYTE BANK0PAH;
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// xdata BANK1 mapping registers
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// maps XDATA VA=(BANK1VA & 0xFE)<<8 to PA=BANK1PAH:L<<9, size - up to BANK2
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__xdata __at 0xFA42 volatile BYTE BANK1VA;
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__xdata __at 0xFA43 volatile BYTE BANK1PAL;
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__xdata __at 0xFA44 volatile BYTE BANK1PAH;
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// xdata BANK2 mapping registers
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// maps XDATA VA=(BANK2VA & 0xFE)<<8 to PA=BANK2PAH:L<<9, size - up to F000
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__xdata __at 0xFA45 volatile BYTE BANK2VA;
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__xdata __at 0xFA46 volatile BYTE BANK2PAL;
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__xdata __at 0xFA47 volatile BYTE BANK2PAH;
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// PRAM/PROM switching with restart
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// value: bit0 =0 - run from PROM, =1 - run from PRAM. Changing this bit causes CPU restart!
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__xdata __at 0xFA48 volatile BYTE PRAMCTL;
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#endif
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