27 Commits

Author SHA1 Message Date
losewayy a02efe36b5 [feat](kt-kernel): add AVX2 RAWINT4 routed-expert LoRA SFT backend (#2243)
* [feat](kt-kernel): add AVX2 RAWINT4 routed-expert LoRA SFT backend

* [fix](kt-kernel): fix RAWINT4 SFT wrapper and clamp gradients

Allow the RAWINT4 production wrapper on AVX2 runtimes and reject shared backward pools before construction. Preserve FP32 clamp decisions across BF16 caches, remove unused configuration state, and cover rectangular dimensions, multiblock dX, clamp boundaries, and production wrapper tasks with tighter LoRA gradient checks.

* [fix](kt-kernel): plumb swiglu_limit through the RAWINT4 SFT python path

The production wrapper hard-zeroed swiglu_limit for every format except MXFP4, and both SFT python gates rejected non-zero values for RAWINT4 even though MOESFTConfig carries the field and the AVX2 kernel implements the clamp in forward plus the gradient mask in backward. RAWINT4_SFT now accepts a finite non-negative swiglu_limit end to end, while the AMX K2 part (which computes plain SiLU) fails fast instead of silently dropping the clamp. The production-wrapper contract test is parametrized over swiglu_limit 0 and 2, a model-config plumb test covers plain and nested text_config shapes, the __main__ entry exercises both limits, and bench_rawint4_sft.py gains --swiglu-limit.
2026-10-12 19:30:24 +08:00
Max 156016c4ef [fix](kt-kernel): size per-NUMA thread counters by physical NUMA id (#2228)
* fix(kt-kernel): size per-NUMA thread counters by physical NUMA id

WorkerPool::init() and NumaJobDistributor::init() indexed the per-NUMA
worker counter by the *physical* NUMA ID while sizing it by the number
of subpools. A subpool mapped to a NUMA node whose ID is >= the subpool
count (e.g. --kt-threadpool-count 1 --kt-numa-nodes 1) therefore read
and wrote out of bounds, shifting the per-node core offset and logging
"Core ... not found" (or corrupting the heap and aborting).

Size the counter vector to cover every NUMA ID present in the subpool
map. Add a CPU regression test that builds two subpools on a
high-numbered NUMA node and verifies the worker thread offsets.

* test(kt-kernel): add single-subpool regression case for #2221

The existing fixture always builds two subpools, so on a dual-socket host
(NUMA IDs [0, 1]) the two-element counter stays in bounds and the old code
passes there. Add a single subpool mapped to a nonzero NUMA node: the size-1
counter is then indexed at an ID >= 1, reproducing #2221 on any multi-NUMA
host. Verified that this case fails/aborts on the unpatched code and passes
with the fix.

Suggested by @f-wunderlich in review.
2026-10-12 12:56:12 +08:00
Mohammad Hijjawi 44fbb184d5 [fix](cli): fill in the model name and path in kt model remove/edit warnings (#2220) 2026-10-12 12:44:24 +08:00
yyj a5d7ad9047 feat(sft) Deepseek v4 flash LoRA (#2216)
* feat(sft): add native MXFP4 routed-expert LoRA kernels

* test(sft): validate DeepSeek V4 MXFP4 routed experts

* feat(sft): AVX2 tier for MXFP4 routed-expert LoRA SFT

MXFP4_SFT_MOE on non-AVX512 builds, same Python contract as the AMX /
AVX512-BF16 kernel from #2185 (KTMoEWrapper(method="MXFP4_SFT")), for
AVX2+FMA+F16C hosts (Zen 2/3 EPYC, older Xeons).

* operators/avx2/sft_mxfp4-moe.hpp: AVX2_SFT_MXFP4_MOE_TP part on top of
  AVX2_MXFP4_MOE_TP (frozen packed E2M1/UE8M0 base, LoRA gate/up/down,
  V4 swiglu clamp, transpose-free packed-weight dX, authoritative LoRA grads).
* operators/moe-sft-tp.hpp: AVX2 result merge; AVX-512 merge loops and the
  block-FP8 staging guarded so the wrapper builds without AVX-512.
* ext_bindings.cpp: bind MXFP4_SFT_MOE -> TP_MOE_SFT<AVX2_SFT_MXFP4_MOE_TP>
  when USE_AMX_AVX_KERNEL is off; MOESFTBindings no longer AMX-only.
* python/sft/backend.py: runtime reports cpu_variant=avx2, kernel avx2-mxfp4-g32.
* test_mxfp4_sft_numerical.py: inference regression uses AVX2MXFP4_MOE when
  AMXFP4_KGroup_MOE is absent.

Validated on 2x EPYC 7452 (AVX2, no AVX-512): test_mxfp4_sft_numerical.py
TP1/TP2 all stages rel-L2 <= 0.4% (limits 3-5%); validate_dsv4_mxfp4_sft_layer.py
on DeepSeek-V4-Flash-0731 layer 3, TP1 and TP2: passed, forward/grad_input/
LoRA grads rel-L2 0.10-0.29%, base weights unchanged.

Note: the build uses -ffast-math, so exp() past the float range is undefined;
the scalar sigmoid tails clamp the argument like the vector path.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_011Mgsduzz2fx1gSvfHbR8RZ

* fix(sft): clamp MXFP4 scalar-tail sigmoid exponent

* feat(sft): integrate native V4 experts with LoRA training and export

Wrap only routed experts while preserving V4 routing and shared branches. Validate native checkpoint provenance and stream a BF16 non-expert cache without dequantizing routed experts.

Add audited static SGLang export and reproducible training, resume and generation acceptance helpers. CPU retain/GPU recompute GAS1/GAS4 smoke and 265 KT regression tests pass; long-run quality and resume acceptance remain in progress.

* fix(sft): retain async inference buffers until CUDA work completes

* test(sft): isolate V4 adapter effects with matched-kernel controls

Allow baseline and non-expert-only exports to retain a zero-B expert adapter so all ablations execute the same native forward kernel. Add paired held-out generation reporting with explicitly diagnostic lexical metrics.

* test(sft): compare PEFT targets semantically during V4 resume audits

* test(sft): cancel queued V4 inference checks after a failed request

* test(sft): preserve raw V4 responses before finite-output validation

* feat: prepare V4 cache atomically and package static adapter export

* build: preserve accepted CUDA carriers across Python ABIs

* test: retain FP8 loading contracts after V4 wrapper integration

* test: exclude historical concatenated-sample smoke from delivery

* test(sft): audit unpacked batches and single-GPU resume state

* docs(sft): align April V4 recipe with approved unpacked delivery

* test: keep frozen-parameter audit indices exact for large tensors

* test: record the loaded native backend in acceptance evidence

* test: timestamp training audit events for startup measurements

* docs: pin V4 serving dependencies and account for reserved token slots

* [refactor](sft): keep V4 follow-up focused on runtime integration

---------

Co-authored-by: 05yuki <ceu.azul.samu@gmail.com>
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
2026-09-30 21:29:43 +08:00
yyj aa2cd3072f [feat] Add native RAWINT4 routed-expert LoRA SFT for Kimi K2.5/K2.6 (#2186)
* [feat](sft): add K2 MoE SFT backend

* [feat](sft): enable packed KGroup backward for K2 SFT

* [feat](serving): add KT LoRA to SGLang adapter converter

* [test]: cover KT SFT and composite LoRA serving paths

* [perf](bench): add reusable KT E2E benchmark harness

* [test](sft): add K2 MoE AMX and real Kimi load smoke cases

* [perf](bench): add K2 SFT packed backward profile harness

* [test](sglang): cover Qwen3.5 LoRA shape filters

* [perf](sft): add K2 forward profiling logs

* [docs](sft): clarify K2 packed backward flow

* [docs](sft): number K2 backward comment steps

* chore: mirror sap4 loader baseline

* Add K2 SFT profiling ranges

* Add backward NVTX ranges for K2 SFT profiling

* perf(sft): add rank8 LoRA backward vector paths

* perf(sft): reuse down LoRA bprop cache

* [perf]: add K2 RAWINT4 prefill mat-mat dispatch

* [perf] Refactor K2 RAWINT4 prefill accumulation

* [perf]: add blocked RAWINT4 prefill backend

Cherry-picked from be40f8e with local amx.py conflict resolution.

* Optimize blocked RAWINT4 decode vecmul

* perf(sft): checkpoint qj5090 packed backward baseline

* perf(sft): batch expert LoRA backward as matmul

* perf(sft): align K2 base backward with BF16 matmul

* Optimize K2 SFT backward workspace path

* docs(sft): hand off RAWINT4 KGroup build and Kimi configs

* [feat](kt-kernel): add Kimi RAWINT4 LoRA SFT kernels

* [feat](kt-kernel): integrate Kimi RAWINT4 LoRA SFT

* [fix](sft): preserve input gradients through frozen routers

Build the routing graph when either activations or router parameters require gradients, while respecting the ambient grad mode. Keep frozen router parameters frozen and reject detached routing weights whenever gradients are needed.

Correct the existing frozen-router expectation and cover input-gradient equivalence for linear, DeepSeek/Kimi and GLM routing, checkpoint reuse, grad modes and detached-output failures.

Validated 62 routing/shared-expert/checkpoint tests on PyTorch 2.9.1 and a two-step Kimi K2.5 RAWINT4 four-GPU S512 LoRA smoke with per-rank routing-input gradient audits.

* [perf](kt-kernel): accelerate RAWINT4 prefill and backward

Reuse decoded weight columns across prefill rows and prepack BF16 backward coefficients into bounded per-worker panels. Use AMX BF16 tiles when available, retaining the AVX512-BF16 path and frozen base weights.

Balance expert work, parallelize cache copies and router reductions, and correct the signed INT4 -8 dot-product boundary. Add a CPU replay benchmark and forward/backward panel regressions.

Validated on sap4 with Kimi K2.5, TP1/TP2 replay, AMX and AVX-512 multi-GPU training, gradient windows, and saved LoRA artifacts. User-facing clean builds and AMD hardware remain separate validation work.

* [fix](sft): limit default OpenMP pools to the CPU owner

Keep the affinity-visible physical-core budget on rank 0 and default non-owner distributed ranks to one thread. Preserve explicit generic and KT-specific thread overrides, including intentional single-thread settings.

Cover single-process behavior, non-owner ranks, repeated configuration, and explicit overrides. The 109 configuration, activation-policy, and backend-dispatch tests pass.

---------

Co-authored-by: yyj <yyj@qj5090.local>
Co-authored-by: djh <jd4136@columbia.edu>
2026-09-10 17:05:16 +08:00
Huang Wensen 6d460cc107 [feat](kt-kernel): packed-int4-resident AVX-VNNI-256 GPTQ INT4 backend (#2187) 2026-09-07 20:20:04 +08:00
yyj e80614fc2d [feat](kt-sft): Activation reuse & Int8 kernel refactor & native block-FP8 LoRA SFT (#2141)
* feat(sft): support distributed activation reuse policies

* feat(sft): add frozen-base INT8 LoRA training

* fix(sft): make INT8 expert LoRA rank-zero authoritative

* fix(sft): preserve DeepSeek router LoRA routing

* feat(sft): enable persistent INT8 LoRA training

* perf(sft): accelerate INT8 VNNI with oneDNN BRGEMM

* perf(int8): fuse oneDNN compensation into backward repack

* [feat]: support BF16 expert LoRA training

* [fix]: honor forwarded activation policy in SFT workers

* feat(sft): add native block-FP8 routed expert LoRA

* feat(sft): expose explicit expert placeholder ownership

* fix(sft): publish fused adapter artifacts atomically

* feat(sft): own artifact and adapter lifecycle contracts

* fix(sft): harden artifact and rank-local contracts

* fix(sft): auto-adapt owner before adapter restore

* style(sft): keep lifecycle comments concise

* fix(sft): require fused adapter manifests

* test(sft): use spawn for distributed workers

* fix(sft): preserve runtime checkpoint metadata

* fix(sft): validate wrapped runtime configuration

* fix(sft): preserve expert format provenance

* fix(sft): own routed experts during device dispatch

* test(sft): lock explicit quantization conflict

* fix(cpu): make shared memory buffers lifetime-safe

* release: prepare v0.7.0
2026-08-17 16:25:14 +08:00
liyuemathematician 168f581676 [feat](sft): support Qwen VLM MoE fine-tuning (#2156) 2026-08-17 10:51:55 +08:00
yyj 924754a00b [feat](kt-kernel): end-to-end full-parameter and LoRA SFT(#2094)
* Add full FT development snapshot

* [fix](kt-kernel): fix Full FT TP base weight gradients

* [fix]: bug fix of 2d81e86

* [fix](kt-kernel): fix AMX BF16 full-weight gradients

* [docs](kt-kernel): document Full FT fork changes and debug history

* [docs](kt-kernel): align fork remote terminology

* [chore](kt-kernel): keep agent notes local

* [fix](kt-kernel): configure SFT OpenMP threads

* [perf](kt-kernel): optimize AMX Full-FT weight gradients

Coarsen base-weight gradient work from individual output tiles to fixed-intermediate strips so each task reuses packed panels across the hidden dimension.

Keep aligned thread-local BF16 panels across tasks and retain FP32 AMX accumulator tiles for the full K reduction. Gate and up run separate K passes while sharing the packed input panel.

On the matched Qwen3-30B-A3B 1-GPU test, stable Full-FT backward drops from 9.281s to 6.792s (-26.82%), step time drops from 19.252s to 16.140s, and TPS rises from 212.76 to 253.78. The LoRA-only backward control changes by -2.74%.

Validated with clang-format, the Release AMX/CUDA extension build, TP1/TP2 reference gradients across boundary token counts, and the 15-step Full-then-LoRA performance run.

* [feat](kt-kernel): add staged SFT profiling

* [fix](kt-kernel): reuse inference BF16 kernel for SFT

* [perf](kt-kernel): add fine-grained Full-FT profiling

* [perf](kt-kernel): batch BF16 Full-FT weight gradients

Use one expert-aggregated tile driver for AVX512-BF16 and AMX base-weight gradients, and pack updated full-precision weights directly into TP BufferB layouts without temporary partitions. Add worker-local profiling and focused dWeight/strided-repack coverage.

* [test](kt-kernel): benchmark BF16 dWeight AMX driver

* [fix](kt-kernel): label dWeight store as worker CPU time

* [docs](sft): record BF16 Full-FT performance

* [docs](sft): remove Qwen3 Full-FT performance report

* [perf](kt-kernel): reduce BF16 Full-FT checkpoint overhead

Retain the first CPU MoE forward state across non-reentrant checkpoint recomputation, write BF16 activations directly into the backward cache, and reduce dWeight packing and gradient-clear traffic. Extend staged profiling and cover checkpoint reuse plus AMX/AVX dWeight paths.

* [perf](kt-kernel): make SFT optimizer gradients authoritative

Bind Full-FT and LoRA Parameter.grad directly to the KT-managed BF16 gradient buffers, avoiding PyTorch duplicate accumulation.

Accumulate microbatch gradients in C++, lazily clear expert buffers between optimizer windows, preserve rank-0 distributed ownership, and add lifecycle and AMX dWeight coverage.

* [perf](kt-kernel): avoid eager Full-FT gradient zeroing

Allocate authoritative Full-FT gradient buffers with torch.empty. The C++ state machine performs the mandatory full clear before first use, avoiding redundant Python-side first touch.

* perf(sft): enable checkpoint forward reuse for LoRA

* fix(sft): serialize checkpoint recompute with async repack

* fix(sft): persist authoritative full weights

* fix(sft): normalize legacy distributed gradients

* [fix](sft): train gated shared experts

* fix(sft): preserve expert placeholders across state dict loads

* ci: publish ktransformers sdist in release workflow

* fix(sft): preserve router autograd for LoRA training

Determine routing graph tracking from the router's trainable parameters instead of the Full-FT mode flag, so PEFT LoRA adapters on MoE gates receive routing-weight gradients. Fail fast when a trainable router returns detached weights and cover frozen, TopK, checkpoint-reuse, and two-step optimizer behavior.

---------

Co-authored-by: illu <wubowen03@foxmail.com>
2026-07-23 21:23:34 +08:00
yyj d1a3ed8a30 [perf]: add K2 RAWINT4 prefill mat-mat dispatch (#2080)
* [perf]: add K2 RAWINT4 prefill mat-mat dispatch

* [perf] Refactor K2 RAWINT4 prefill accumulation

---------

Co-authored-by: yyj6666667 <yyj6666667@users.noreply.github.com>
2026-07-19 21:43:01 +08:00
Aaryan Mehta 937f61c988 [fix](kt-kernel): AVX-VNNI-256 RAWINT4 per-expert weight loading (#2092) 2026-07-19 17:24:52 +08:00
callmegaga 0c2912a5e2 [feat] Add SYCL backend for intel iGPU (#2089)
* [feat](sycl): add sycl backend for igpu

* [feat](sycl): improve prefill

* [feat](sycl): finish and test sycl gptq int4
2026-07-17 16:24:04 +08:00
VectorPeak cb9f47d142 [fix](cli): detect bound ports before launch (#2071)
* [fix](cli): detect bound ports before launch

* [fix](cli): align port reuse check by platform
2026-07-06 18:25:31 +08:00
lutianshu824 79b265b2f6 fix: normalize compressed RAWINT4 weights (#2075)
* fix: normalize compressed RAWINT4 weights

* docs: add Hygon DCU ROCm notes

---------

Co-authored-by: lutianshu824 <lutianshu824@users.noreply.github.com>
2026-07-06 18:06:52 +08:00
Dayuxiaoshui 7641f5445d [feat] : Add MACA backend support for kt-kernel and fix CPU MoE tests (#2044)
* Add MACA backend support for kt-kernel

* Add MACA event API mappings

* Fix AMX build flags and CPU MoE tests


---------

Co-authored-by: <Engle_Chaveztih@sociologist.com>
2026-06-16 16:49:06 +08:00
devangpratap 89d30a3d01 [fix(loader)]: correct off-by-one expert-count guard in load_experts (#2026)
* [fix(loader)]: correct off-by-one expert-count guard in SafeTensorLoader.load_experts

After the discovery loop, max_experts_count is the highest expert index found
(expert count - 1), and is -1 only when the key has no experts. The guard
checked == 0, which falsely rejected single-expert layers and silently returned
empty weight lists for the zero-expert case. Check == -1 instead.

Adds a CPU regression test covering the single-, zero-, and multi-expert cases.

* [test(loader)]: import loader as a top-level module in expert-count guard test

Per review feedback: add python/utils to sys.path and import loader directly
instead of the importlib.util boilerplate. Still bypasses utils/__init__.py
(and the compiled kt_kernel_ext) while keeping the import idiomatic.
2026-06-07 23:41:04 +08:00
Jiaheng Dai c9a915e6ac [feat](kt-lora): add end-to-end Qwen3.5 MoE KT LoRA serving workflow (#2031)
* [feat](kt-lora): add KT expert LoRA adapter serving

* [feat]: pin Qwen3.5 non-expert LoRA support

* [feat](kt-lora): add merged SGLang adapter workflow

Document the KT SFT to SGLang serving loop and extend the converter with optional split outputs so users can serve one merged adapter while retaining debug-friendly expert/non-expert artifacts.

Co-authored-by: Cursor <cursoragent@cursor.com>

* [fix](kt-lora): validate adapter conversion

Co-authored-by: Cursor <cursoragent@cursor.com>

---------

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-06-05 16:57:14 +08:00
Aliez Ren 02be2bf53f [feat](kt-kernel): add AVX2/AVX-VNNI RAWINT4 MoE backend (#1942)
* [feat](kt-kernel): add AVX2/AVX-VNNI RAWINT4 MoE backend

* Update AVX2 tutorial with AVX2 compilation instructions

Added instructions for forcing AVX2 compilation on AVX512 or AMX machines.

* Add instructions for AVX2 compilation

---------

Co-authored-by: Jiaheng Dai <108478605+jdai0@users.noreply.github.com>
2026-04-30 17:16:49 +08:00
callmegaga a9411f1d72 Supports vnni-256 for GPTQ INT4 (#1926)
* [feat](kt-kernel): support avx-vnni-256 for gptq int4
2026-04-13 17:59:59 +08:00
mrhaoxx 7a9daf0cd4 [feat](kt-kernel): support avx2 only inference for bf16 fp8 and gptq int4 (#1892)
* feat: support avx2 bf16 fp8 inference

* feat: support avx2 gptq int4 inference

* fix: numeric issues in fp8 dequant

* Tutorial avx2 (#1900)

* fix: prevent injecting -DLLAMA_AVX512=ON on AVX2-only machines

* docs: add AVX2 tutorial for running KTransformers on AVX2-only CPUs

* Tutorial avx2 (#1901)

* fix: prevent injecting -DLLAMA_AVX512=ON on AVX2-only machines

* docs: add AVX2 tutorial for running KTransformers on AVX2-only CPUs

* docs: update README.md

---------

Co-authored-by: Benjamin F <159887351+yyj6666667@users.noreply.github.com>
2026-03-27 14:45:02 +08:00
Jianwei Dong 027832c590 [feat](kt-kernel): CPU-GPU experts sched (#1796) 2026-01-16 17:01:15 +08:00
ErvinXie d8046e1bb4 Kt minimax (#1742)
[feat]: fp8 kernel and kt-cli support
2025-12-24 15:39:44 +08:00
Jianwei Dong 1f79f6da92 [feat](kt-kernel): Add automatic deployment workflow (#1719) 2025-12-16 15:20:06 +08:00
ZiWei Yuan c2b8c60c4e [ci]: add int4_1 & int4_1k (#1653)
* [feat]: init amd adaption

* [feat]: add blis support

* [fix]: fix setup and moe kernel warpper

* [fix](setup.py): support rebuild with cache and import kt_kernel works
fine

* [feat]: add moe_kernel converter for amd and implement the load
method(haven't tested yet)

* [feat](moe_kernel/moe.hpp): delete unused memory when using save

* [fix](moe_kernel): update PLAIN for pack

* [fix](moe_kernel): rm printf debug

* [fix](moe_kernel): skip gpu experts

* [fix](moe_kernel/moe.hpp): update include memory path

* [feat](moe_kernel/moe.hpp): support expert deferral

* [feat]: finish amd

* [ci]: add int4_1 & int4_1k

---------

Co-authored-by: mrhaoxx <mr.haoxx@gmail.com>
2025-12-02 15:58:14 +08:00
Jianwei Dong c256150e08 update ci test (#1647) 2025-11-27 16:39:48 +08:00
Jianwei Dong fef6dd98a8 add accuracy and performance test (#1643) 2025-11-27 10:56:39 +08:00
Jianwei Dong 51745a9ea1 add ci (#1642) 2025-11-25 20:52:08 +08:00