Commit Graph

78 Commits

Author SHA1 Message Date
柚木 鉉 1679a50c2d add support for riscv32+rvv1.0 (rv32 and rv64ilp32) with c907 support (#6280)
* add support for riscv32+rvv1.0 (rv32 and rv64ilp32) with c907 support

* add new action linux rv32 and some fix
1. add new action linux rv32
2. add new toolchains c907-v310 for lp64d
3. fix action paths check
2025-08-25 14:12:30 +08:00
Copilot 4644540ea4 Add Windows XP support merging PRs #6176 and #6177 (#6204)
Co-authored-by: Sugar-Baby <87747602+Sugar-Baby@users.noreply.github.com>
Co-authored-by: AtomAlpaca <66774326+AtomAlpaca@users.noreply.github.com>
2025-07-24 15:45:02 +08:00
nihui 091f7da5ba update spacemit toolchain and qemu test (#6200) 2025-07-23 17:25:09 +08:00
Christopher 260f493ada add cross toolchain cmake config of AK3918(AK) and SS928(hisi) (#6164) 2025-07-10 19:23:45 +08:00
nihui abf0de4488 update ruapu to detect zfh zvfh xtheadvector (#5841)
* always prefer xtheadvector
* update ci toolchain
2025-06-14 14:54:04 +08:00
nihui b969f3978d update test-coverage ci (#6040) 2025-05-09 11:35:44 +08:00
nihui f7e6411a01 fix riscv ci c906/c908/c910/k1 static linking (#5971) 2025-04-02 16:41:24 +08:00
Zhuo Zhang 23cdc817ca refactor qnx cmake toolchain files (#5961)
* Support multiple QNX SDP versions: 700, 710, 800, etc

* Support windows and linux hosts when find programs like C/C++ compilers

* Better hint message by recommend users invoking QNX SDP bundled script

* Precise to aarch64 in file naming

* Update how-to-build.md QNX section
2025-03-31 10:43:27 +08:00
nihui eb7e92a50e add riscv spacemit x60 ci (#5852) 2024-12-25 16:09:40 +08:00
nihui 2a804078d6 add riscv c908 ci (#5850) 2024-12-25 14:26:23 +08:00
nihui 19caca3140 port rvv intrinsic 1.0+ (#5642)
* zfh zvfh xtheadvector infra
* dispatch for rvv and xtheadvector
* dispatch for non-vector zfh
* port xtheadvector recp rsqrt trunc
* general rvv gemm
* c906 and c910 ci
* old tuple code clean
* update riscv64 ci
* update build doc
* drop old th1520 toolchain
2024-12-04 16:16:17 +08:00
luxincn 02327ba96f add esp32 build document and ci Refs #5536 (#5567) 2024-07-09 11:03:05 +08:00
nihui fafb897ff7 update ios toolchain, add visionos ci, update watchos, ncnn target ilp32 (#5399) 2024-04-03 11:05:32 +08:00
Zhuo Zhang 54e58bfaf5 Improve cmake toolchain files (#5144)
* [style] Use same style for cmake `set` command
* [build] Specify CMAKE_FIND_ROOT_PATH_MODE_PACKAGE in xxx.toolchain.cmake
* [build] Allow user passing args for cmake find cmds
2023-11-13 17:25:08 +08:00
nihui 31e315981a watchos and tvos ci (#5124) 2023-11-01 19:14:31 +08:00
nihui 39bc71c941 support big endian platform, add powerpc ci (#5121) 2023-11-01 14:55:01 +08:00
邓实诚 a1e3ebf8e5 implement simplemath (#4905)
* complete abs, fmod and sin function in simplemath.h

* remove some unused variables in simplemath.cpp

* modify test-coverage.yml and add some functions to simplemath.cpp

* modify erf.cpp which included math.h

* include platform.h for NCNN_SIMPLEMATH definition

* move utility constants and functions in simplemath.h to simplemath.cpp

* guard simplemath functions with extern "C"

* add NCNN_EXPORT macro in simplemath.h

* include plateform.h and guard all declarations with NCNN_SIMPLEMATH

* clean unused code in test_unaryop.cpp

* guard #include <vector> with NCNN_SIMPLEMATH in benchncnn.cpp

* add 'static' to guard functions that not declarated in header file

* modify sin and cos with better implementation

---------

Co-authored-by: HonestDeng <HonestDeng@users.noreply.github.com>
2023-10-23 10:51:51 +08:00
JeremyRand 0a8cf31a05 Add POWER8 VSX toolchains (#4853)
* Add POWER8 VSX toolchains

POWER8, though slower than POWER9, is still used in the wild; these
toolchains should still be much faster on POWER8 than POWER8 without VSX
optimizations.

* VSX toolchains: set -cpu arg in QEMU CI tests
2023-08-06 22:16:34 +08:00
JeremyRand 472244420e VSX toolchains: check for SSE2 support (#4845)
Improves compatibility with Clang 11.

Also rename NCNN_SSE* options to NCNN_VSX_SSE* to avoid conflict between
x86 and POWER (went unnoticed before because x86 doesn't have an option
for toggling SSE 4.1).

Co-authored-by: Jeremy Rand <jeremyrand@danwin1210.de>
2023-07-11 15:56:51 +08:00
JeremyRand 47e0daf4a1 Translate x86_64 SSE to ppc64le VSX intrinsics (#4807)
* Add POWER9 VSX toolchains

Translating x86_64 SSE to ppc64le VSX intrinsics yields a quite large
speedup on POWER9. See this article for background:

https://www.talospace.com/2019/07/easier-power-vectorizing-for-fun-and.html

* Add power9le docs

* power9le clang toolchain: Document Clang 13+ requirement

---------

Co-authored-by: Jeremy Rand <jeremyrand@danwin1210.de>
2023-07-06 16:02:05 +08:00
nihui d294b26783 add qnx710.toolchain.cmake (#4706) 2023-05-08 16:40:56 +08:00
Zhuo Zhang b709f041fe Add qnx.toolchain.cmake (#4213) 2023-05-08 16:33:41 +08:00
nihui 490816b21b update ios toolchain, simulator arm64 ci, mac catalyst ci (#4697) 2023-05-06 18:14:19 +08:00
nihui 6019f47f08 ci loongarch64 lsx (#4344) 2022-11-11 20:52:22 +08:00
陸 言 0f38cb2cd8 Add TH1520 (4*C910V) toolchain support. (#4267) 2022-10-13 13:11:22 +08:00
Xavier Hsinyuan e7eadca6c1 RVV: use new interface for segment load/store & change word_type to size_t&add clang ci (part #4100) (#4118)
* RVV: use size_t for vl

* RVV: replace vsseg.v tuple type by using regex

-----

search:
vsseg([1-9])e(8|16|32)_v_(f|i|u)\2m(1|2|4|8)x\1\(([ -~]+), vcreate_\3\2m\4x\1\(([ -~]+)\), vl\);

substitute by:
vsseg$1e$2_v_$3$2m$4($5, $6, vl);

* RVV: replace vssseg.v tuple types by using regex

---

search:
vssseg([1-9])e(8|16|32)_v_f\2m1x\1\(([ -~]+), vcreate_f\2m1x\1\(([ -~]+)\), vl\);

substitute by:
vssseg$1e$2_v_f$2m1($3, $4, vl);

* RVV: replace vlseg.v tuple types in load/store

* RVV: replace vloxseg2ei32.v tuple types

* RVV: add a wrapper for old compilers

* RVV: add segment load/store wrapper in pakcing

* RVV: fix cmake test

* RVV: make clang happy by dropping VLAs in sgemm

* RVV: add clang cmake toolchain configure

* RVV: add clang ci, riscv64-unknown-linux-gnu

Co-authored-by: thelastlin <thelastlin@users.noreply.github.com>
Co-authored-by: nihui <shuizhuyuanluo@126.com>
2022-10-01 21:24:37 +08:00
nihui b4ba207c18 more strict compiler rvv checks, drop rvv-071 support (#4094) 2022-07-28 17:47:27 +08:00
nihui e64245c44a ci x86 no sse, do not force sse2 for x86 32bit toolchain (#4043) 2022-07-19 20:24:26 +08:00
nihui c5bb0e52ed add ingenic-x2000 toolchain file 2022-07-13 21:32:35 +08:00
陸 言 cae8d0f1d7 Add Loongson 2F toolchain support (refer to AOSC) (#3992) 2022-07-09 21:45:07 +08:00
nihui 1fd7138d2f armv7 vfpv4 infrastructure (#3929)
* armv7 vfpv4 infrastructure
* optional fp16 format ieee
* arm neon assembly optimization for cast fp16/bf16
2022-06-20 16:25:26 +08:00
nihui d373407bcb add c906 c910 v240 toolchain 2022-05-29 20:50:35 +08:00
nihui f79073c182 update how-to-build doc for raspberrypi and d1 2022-05-19 22:07:10 +08:00
Xavier Hsinyuan 29b6a32ac0 RVV: follow intrinsic doc, replace vfredsum_* with vfredusum_* (#3790)
* RVV: follow intrinsic doc, vfredusum -> vfredsum

* C906: change toolchains for vfredusum

* RVV: test compiler for vfredusum_vs_*
2022-05-15 21:51:49 +08:00
jasonZhang 2b0064c3db fix armv7 platform build tests error (#3710) 2022-04-16 13:05:36 +08:00
nihui 5b7268d95f loongarch64 ci (#3455) 2022-04-12 15:12:47 +08:00
nihui c0a94cd9ca fix armv7 without neon (#3514) 2022-01-18 23:15:54 +08:00
nihui 3a83704c38 binary4d, unary4d (#3443) 2021-12-28 23:13:44 +08:00
Zhuo Zhang 880e2805fe add c906 v223 toolchain (#3449) 2021-12-27 10:27:08 +08:00
nihui 64ba12be23 add c906 v2.2.2 toolchain 2021-12-04 15:36:12 +08:00
Martin Han 7633257ac5 Add support to Ingenic X2000 & T40 CPU (#3343)
* Support Ingenic X2000 & T40

T40 claimed to have MIPS32R2 with MSA, but tested not working on my unit, so set to mips32r2 without MSA.

* Add Ingenic T40XP benchmark result
2021-11-13 13:27:35 +08:00
tsuibin 1699aaaca6 added support for loongarch64 (#3094)
Co-authored-by: tsuibin <tsuibin@loongson.cn>
2021-07-20 10:44:27 +08:00
nihui 1f49fc4b67 mips msa optimization for padding packing flatten innerproduct convolution convolutiondepthwise general cases 2021-07-04 16:00:01 +08:00
nihui b8e03ced3c allow examples building with simpleocv 2021-07-03 11:57:08 +08:00
nihuini 26ea87cc25 do not define android macro for jetson, fix #2939 2021-05-24 11:11:11 +08:00
nihui 655fb3b5eb fix rv64gcv test coverage build 2021-05-05 17:29:05 +08:00
nihui 11958424c2 runtime riscv v and zfh dispatch, riscv v optimization for cast 2021-05-05 17:07:40 +08:00
nihui 48d5dbf33f ci riscv rvv coverage (#2886) 2021-05-04 22:02:30 +08:00
Zhang Xianyi a1ece94f51 Use RVV spec 0.7.1 for C906. (#2868) 2021-04-27 07:27:07 +08:00
nihui 45bf3cd779 add runtime riscv v detection function, the initial c906 riscv linux toolchain 2021-04-24 15:35:17 +08:00