Fix typo

2026-10-16 21:50:36 +08:00 · 2021-10-06 16:29:37 +08:00
parent af834afccb
commit e51927b41b
49 changed files with 177 additions and 178 deletions
@@ -34,7 +34,7 @@ To make it easier to download, each HTML page contains embedded CSS and images.
 ** https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol3-EN.pdf[PDF version].
 ** https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol3-v1.00-CN.pdf[Original document].

-* Loongson 3A5000/3B5000 Registers Technical Reference Manual - Multicore Processor Architecture, Register Descriptions and System Software Programming Guide: This manual introduces the Loongson 3A5000/3B5000 multicore processor architecture and register descriptions.
+* Loongson 3A5000/3B5000 Processor Reference Manual - Multicore Processor Architecture, Register Descriptions and System Software Programming Guide: This manual introduces the Loongson 3A5000/3B5000 multicore processor architecture and register descriptions.
 ** https://loongson.github.io/LoongArch-Documentation/Loongson-3A5000-usermanual-EN.html[HTML version].
 ** https://loongson.github.io/LoongArch-Documentation/Loongson-3A5000-usermanual-EN.pdf[PDF version].
 ** https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-v1.02-CN.pdf[Original document].
@@ -6,8 +6,9 @@ namespace :book do

    desc 'generate contributors list'
    task :generate do |t|
+        ENV["LC_ALL"] = "C"
        puts 'Generating contributors list...'
-        `git shortlog --summary --email HEAD | grep -v -E "users\.noreply\.github\.com" | cut -f 2- | LC_ALL=C sort --ignore-case > contributors.txt`
+        `git shortlog --summary --email HEAD | grep -v -E "users\.noreply\.github\.com" | cut -f 2- | sort --ignore-case > contributors.txt`
        puts ' -- contributors list generation done!'
    end

@@ -1,4 +1,4 @@
-= Loongson 3A5000/3B5000 Registers Technical Reference Manual - Multicore Processor Architecture, Register Descriptions and System Software Programming Guide
+= Loongson 3A5000/3B5000 Processor Reference Manual - Multicore Processor Architecture, Register Descriptions and System Software Programming Guide
 Loongson Technology Corporation Limited
 v1.03
 :title-separator: -
@@ -1,7 +1,7 @@
 [[accessing-by-configuration-register-instructions-1]]
 ==== Accessing by Configuration Register Instructions

-In addition to the traditional per-address access mode, the 3A5000 also supports access to private frequency division configuration registers using the configuration register instruction.
+In addition to the legacy per-address access mode, the 3A5000 also supports access to private frequency division configuration registers using the configuration register instruction.

 Note that the private frequency division configuration register control is mutually exclusive with the original processor core software frequency division setup register control, and only one of the two can be used.
 The choice is made by using the corresponding bit on the other function configuration register.
@@ -78,7 +78,7 @@ d|Reset Value
 |Flat Mode
 |R
 |1'b0
-|Traditional compatibility mode
+|Legacy compatibility mode

 |11
 |Guest Mode
@@ -1,7 +1,7 @@
 [[local-interrupts-handling]]
 ==== Local Interrupts Handling

-In the traditional interrupt handling model, all interrupts are stored by the interrupt vector inside the HT controller and then distributed through the interrupt line of the HT controller connected to the interrupt router on the chip.
+In the legacy interrupt handling model, all interrupts are stored by the interrupt vector inside the HT controller and then distributed through the interrupt line of the HT controller connected to the interrupt router on the chip.
 In this case, HT interrupts are only available to CPU cores through a limited number of connections, and cannot be distributed across chips, so the usage scenario is rather limited.

 In this HT interrupt mode, when performing interrupt processing, the interrupt router on the chip is transparent to the software and the core goes directly to the interrupt vector of the HT controller (typically `0x90000efdfb000080`) for lookup and then per-bit processing.
@@ -2,9 +2,9 @@
 == I/O Interrupts

 The Loongson 3A5000 chip supports two different interrupt methods.
-The first is the traditional interrupt method, which is compatible with processors such as the 3A3000, and the second is the new extended I/O interrupt method, which is used to support the interrupt cross-chip and dynamic distribution functions of the HT controller.
+The first is the legacy interrupt method, which is compatible with processors such as the 3A3000, and the second is the new extended I/O interrupt method, which is used to support the interrupt cross-chip and dynamic distribution functions of the HT controller.
 The following describes each of the two interrupt methods.

-include::io-interrupts/traditional-io-interrupts.adoc[]
+include::io-interrupts/legacy-io-interrupts.adoc[]

 include::io-interrupts/extended-io-interrupts.adoc[]
@@ -1,7 +1,7 @@
 [[extended-io-interrupts]]
 === Extended I/O Interrupts

-In addition to being compatible with the traditional I/O interrupt method, the 3A5000 supports extended I/O interrupts, which are used to distribute 256-bit interrupts on the HT bus directly to each processor core instead of forwarding them through the HT interrupt line, increasing the flexibility of I/O interrupt usage.
+In addition to being compatible with the legacy I/O interrupt method, the 3A5000 supports extended I/O interrupts, which are used to distribute 256-bit interrupts on the HT bus directly to each processor core instead of forwarding them through the HT interrupt line, increasing the flexibility of I/O interrupt usage.

 Before the core can use the extended I/O interrupt, it needs to enable the corresponding bit in the "`Other function configuration register`".
 This register has a base address of `0x1fe00000`,It can also be accessed using the configuration register instruction (IOCSR), an offset address of `0x0420`.
@@ -32,4 +32,4 @@ include::extended-io-interrupts/accessing-by-configuration-register-instructions

 include::extended-io-interrupts/extended-io-interrupt-trigger-register.adoc[]

-include::extended-io-interrupts/difference-in-handling-between-extended-io-interrupts-and-traditional-ht-interrupts.adoc[]
+include::extended-io-interrupts/difference-in-handling-between-extended-io-interrupts-and-legacy-ht-interrupts.adoc[]
@@ -152,9 +152,9 @@ d|Offset Address
 |Interrupt status of extended I/O interrupt `[255:192]` routed to processor core 3
 |===

-Similar to traditional I/O interrupts, the 256-bit interrupt source for Extended I/O interrupts can be software-configured to select the target processor core for the desired interrupt.
+Similar to legacy I/O interrupts, the 256-bit interrupt source for Extended I/O interrupts can be software-configured to select the target processor core for the desired interrupt.

-However, the interrupt sources are not individually selected to route to any of the processor core interrupts INT0 through INT3, but rather the routing of INT interrupts is done in groups. 
+However, the interrupt sources are not individually selected to route to any of the processor core interrupts INT0 through INT3, but rather the routing of INT interrupts is done in groups.
 The following are the interrupt pin routing registers configured by group.

 Starting with the 3A5000, the interrupt pin routing bits have been added in a coded manner and are enabled by the `CSR[0x420][49]` bit control.
@@ -1,15 +1,15 @@
-[[difference-in-handling-between-extended-io-interrupts-and-traditional-ht-interrupts]]
-==== Difference in Handling Between Extended I/O Interrupts and Traditional HT Interrupts
+[[difference-in-handling-between-extended-io-interrupts-and-legacy-ht-interrupts]]
+==== Difference in Handling Between Extended I/O Interrupts and Legacy HT Interrupts

-With traditional HT interrupt processing, HT interrupts are processed internally by the HT controller and mapped directly to the `256` interrupt vectors on the HT configuration registers, and then the `256` interrupt vectors are grouped to generate `4` or `8` interrupts that are routed to the various processor cores.
-Due to the traditional interrupt line connection, no cross-chip interrupts can be generated directly, so all HT I/O interrupts can only be handled directly by a single chip.
+With legacy HT interrupt processing, HT interrupts are processed internally by the HT controller and mapped directly to the `256` interrupt vectors on the HT configuration registers, and then the `256` interrupt vectors are grouped to generate `4` or `8` interrupts that are routed to the various processor cores.
+Due to the legacy interrupt line connection, no cross-chip interrupts can be generated directly, so all HT I/O interrupts can only be handled directly by a single chip.
 On the other hand, the interrupts distributed by the hardware within the chip are only in units of the final `4` or `8` interrupts and cannot be handled on a bit-by-bit basis, which leads to the problem of poor hardware interrupt distribution.

 With the extended I/O interrupt method, HT interrupts are sent directly from the HT controller to the chip's interrupt controller for processing, and the interrupt controller can directly get `256` Instead of the previous `4` or `8` interrupts, each of these 256-bit interrupts can be routed and distributed independently, and can be distributed and rotated across slices.

-With Extended I/O interrupts, the software processing is slightly different than with traditional HT interrupts.
+With Extended I/O interrupts, the software processing is slightly different than with legacy HT interrupts.

-With traditional HT interrupts, the kernel looks directly at the interrupt vector of the HT controller (typically `0x90000efdfb000080`) and then processes the interrupts by bit, regardless of how the routing mode is configured.
+With legacy HT interrupts, the kernel looks directly at the interrupt vector of the HT controller (typically `0x90000efdfb000080`) and then processes the interrupts by bit, regardless of how the routing mode is configured.

 After using Extended I/O interrupts, the cores go directly to the Extended I/O status register (configuration space `0x1800`) to read the interrupt status for processing.
 Each core will only read the interrupt's own interrupt status and process it, and there will be no interference between different cores.
@@ -1,5 +1,5 @@
-[[traditional-io-interrupts]]
-=== Traditional I/O Interrupts
+[[legacy-io-interrupts]]
+=== Legacy I/O Interrupts

 The legacy interrupts on the Loongson 3A5000 chip support `32` interrupt sources managed in a unified manner as shown in the figure below.
 Any of the I/O interrupt sources can be configured to enable or disable, how it is triggered, and the target processor core interrupt pin to be routed.
@@ -161,6 +161,6 @@ m|31:24

 Similar to inter-processor interrupts, the base address of I/O interrupts can also be accessed using `0x1fe00000`, or through the processor core's dedicated register configuration instructions.

-include::traditional-io-interrupts/accessing-by-address.adoc[]
+include::legacy-io-interrupts/accessing-by-address.adoc[]

-include::traditional-io-interrupts/accessing-by-configuration-register-instructions.adoc[]
+include::legacy-io-interrupts/accessing-by-configuration-register-instructions.adoc[]
@@ -4,8 +4,8 @@
 The functional features of the Loongson instruction set implemented in the Loongson 3A5000 can be dynamically confirmed by the Loongson instruction set attribute identification mechanism.

 The CPUCFG instruction is a user-state instruction, which is used as CPUCFG rd, rj, where the source operand rj register holds the register number of the configuration information word to be accessed, and the returned configuration word information is written to the rd register, each configuration information word contains up to 32 bits of configuration information.
- For example, bit 0 of configuration word 1 indicates whether the LA32 architecture is implemented, then this configuration information is expressed as CPUCFG.1.LA32[bit0], where 1 means that the font size of the configuration information word is 1, LA32 means that the helper name of this configuration information field is LA32, and bit 0 means that the field LA32 is located in bit 0 of the configuration word. 
- If the configuration information needs to be expressed in multiple bits, then the location information will be recorded in the form of bitAA:BB, which means the consecutive (AA-BB+1) bits from the AAth to the BBth bit of the configuration information word.
+For example, bit 0 of configuration word 1 indicates whether the LA32 architecture is implemented, then this configuration information is expressed as CPUCFG.1.LA32[bit0], where 1 means that the font size of the configuration information word is 1, LA32 means that the helper name of this configuration information field is LA32, and bit 0 means that the field LA32 is located in bit 0 of the configuration word.
+If the configuration information needs to be expressed in multiple bits, then the location information will be recorded in the form of bitAA:BB, which means the consecutive (AA-BB+1) bits from the AAth to the BBth bit of the configuration information word.

 The following table gives a list of configuration information for the instruction set functions implemented in the 3A5000.
 The last column, "`Possible Value`", indicates a possible value to be read from this register, but does not imply that this is the value to be read from the 3A5000 processor.
@@ -1,7 +1,7 @@
 [[guide-to-the-use-of-spi-dual-quad-mode]]
 ==== Guide to the Use of SPI Dual/Quad Mode

-In addition to the traditional single-wire mode, the SPI controller also supports two operating modes, dual mode and quad mode, for booting from the SPI FLASH.
+In addition to the legacy single-wire mode, the SPI controller also supports two operating modes, dual mode and quad mode, for booting from the SPI FLASH.
 The SPI controller can be put into dual mode by setting the `dual_io` register, and quad mode by setting the `quad_io` register.
 The configuration code for these two registers can be added to the first few instructions of the BIOS code, and then the controller will be pointed to the corresponding operating mode after the configuration is completed, which can improve the boot-up speed.

@@ -2,7 +2,7 @@
 == Software Clock System

 Several different levels of usage are defined in the Loongson 3A5000 processor for the clocks used by the system software.
-Inside the processor core are the traditional counter/compare registers, the stable counter registers, and the chip-level node counter registers.
+Inside the processor core are the legacy counter/compare registers, the stable counter registers, and the chip-level node counter registers.

 The following is introductions to stable counter and node counter.

@@ -49,7 +49,7 @@ d!Description
 !CLKSEL[7:6]
 !`2'b00` indicates that PHY clock frequency is `1.6GHz`

-`2'b01` indicates that PHY clock frequency is `6.4GHz` 
+`2'b01` indicates that PHY clock frequency is `6.4GHz`

 `2'b10` Reserved

@@ -23,8 +23,8 @@ Size: `32` bits
 |R/W
 |Reserved

-|1	
-|ht_hi_clken	
+|1
+|ht_hi_clken
 |R/W
 |`HT` Controller `1` Clock Enable

@@ -32,8 +32,8 @@ Size: `32` bits

 `1`: Turn on the clock

-|0	
-|ht_lo_clken	
+|0
+|ht_lo_clken
 |R/W
 |HT Controller `0` Clock Enable

@@ -50,10 +50,10 @@ Default value: `000a_a800h`

 Size: `32` bits

-This register is used to configure the routing information for the device's DMA accesses (i.e., the destination processor for the `DMA` access and the HT controller through which it passes). 
-Since the HT bus only supports `40`-bit addresses and the processor space (and the DMA access space) supports `64`-bit addresses, the addresses need to be transformed before and after passing through the HT bus in order to preserve the address routing information. This feature requires two supports: 
+This register is used to configure the routing information for the device's DMA accesses (i.e., the destination processor for the `DMA` access and the HT controller through which it passes).
+Since the HT bus only supports `40`-bit addresses and the processor space (and the DMA access space) supports `64`-bit addresses, the addresses need to be transformed before and after passing through the HT bus in order to preserve the address routing information. This feature requires two supports:

-. the bridge chip stores the node number information in a certain number of bits of the HT bus address; 
+. the bridge chip stores the node number information in a certain number of bits of the HT bus address;

 . on the processor side, the node information is remapped to the processor's node bit field using the address translation function of the HT receive window.

@@ -68,17 +68,17 @@ The LS7A1000 implements the `DMA` access node number translation function, which
 |Read/Write
 |Description

-|31:16	
-|dma_dest_ht	
+|31:16
+|dma_dest_ht
 |R/W
-|`DMA` access destination node routing configuration. There are 16 nodes, each bit corresponds to a node number. `bit31-16` correspond to `DMA` accesses to nodes `15-0` respectively. 
+|`DMA` access destination node routing configuration. There are 16 nodes, each bit corresponds to a node number. `bit31-16` correspond to `DMA` accesses to nodes `15-0` respectively.

 `1`: Routed to HT controller `1`

 `0`: Routed to HT controller `0`

-|15:13	
-|dma_node_id_offset_ma pped	
+|15:13
+|dma_node_id_offset_ma pped
 |R/W
 |Address Offset of the mapped `DMA` access node number in the HT address space (relative to bit32).

@@ -102,8 +102,8 @@ This register determines the maximum address range for `DMA` accesses to a singl
 |R/W
 |Reserved

-|3:0	
-|dma_node_id_mask	
+|3:0
+|dma_node_id_mask
 |R/W
 |Node number mask for `DMA` accesses. This register determines the number of nodes that can be accessed by device `DMA` access.

@@ -1,7 +1,7 @@
 [[memory-capacity-configuration-register]]
 === Memory Capacity Configuration Register

-This set of registers is used to configure the capacity of the video memory. This register represents the mask of the memory BAR register, 0 means the corresponding bit of the memory BAR register is writable, 1 means not writable. 
+This set of registers is used to configure the capacity of the video memory. This register represents the mask of the memory BAR register, 0 means the corresponding bit of the memory BAR register is writable, 1 means not writable.
 The number of 1's represents the memory capacity. The default memory capacity is 256MB.

 Address Offset: `3838`-`383Bh`
@@ -20,8 +20,8 @@ This register contains configuration information related to pin multiplexing.
 |Read/Write
 |Description

-|31	
-|uart3_enable	
+|31
+|uart3_enable
 |R/W
 |`UART` operating mode selection for pin `UART_RI/DCD` (when selected as `UART` mode)

@@ -29,8 +29,8 @@ This register contains configuration information related to pin multiplexing.

 `1`: Operates in two-wire UART3 mode

-|30	
-|uart2_enable	
+|30
+|uart2_enable
 |R/W
 |UART operating mode selection for pin UART_DTR/DSR (when selected as UART mode)

@@ -38,8 +38,8 @@ This register contains configuration information related to pin multiplexing.

 `1`: Operates in two-wire UART2 mode

-|29	
-|uart1_enable	
+|29
+|uart1_enable
 |R/W
 |UART operating mode selection for pin UART_RTS/CTS (when selected as UART mode)

@@ -47,8 +47,8 @@ This register contains configuration information related to pin multiplexing.

 `1`: Operates in two-wire UART1 mode

-|28	
-|uart0_full_func	
+|28
+|uart0_full_func
 |R/W
 |UART operating mode selection for pin UART_TXD/RXD (when UART mode is selected)

@@ -60,8 +60,8 @@ When bit[31:29] is not equal to 0, regardless of the value of this bit, UART_TXD

 operates in two-wire UART mode regardless of the value of the bit.

-|27	
-|clkoutflex_sel	
+|27
+|clkoutflex_sel
 |R/W
 |Operating mode selection for pin CLKOUTFLEX

@@ -69,8 +69,8 @@ operates in two-wire UART mode regardless of the value of the bit.

 `1`: Operates in CLKOUTFLEX mode

-|26	
-|clkout25m_sel	
+|26
+|clkout25m_sel
 |R/W
 |Operating mode selection for pin CLKOUT25M

@@ -78,8 +78,8 @@ operates in two-wire UART mode regardless of the value of the bit.

 `1`: Operating in CLKOUT25M mode

-|25	
-|lpc_sel	
+|25
+|lpc_sel
 |R/W
 |Operating mode selection for LPC pins (LPC_AD0-3/LPC_SERIRQ/LPC_FRAMEn)

@@ -87,8 +87,8 @@ operates in two-wire UART mode regardless of the value of the bit.

 `1`: Working in LPC mode

-|24	
-|uart_dtr_dsr_sel_i2 c	
+|24
+|uart_dtr_dsr_sel_i2 c
 |R/W
 |Operating mode selection for pin UART_DTR/DSR (determined together with bit20)

@@ -100,8 +100,8 @@ x1b: working in UART mode (decided by bit[31:28] whether to work in full functio

 10b: working in I2C mode

-|23	
-|uart_ri_dcd_sel_i2c	
+|23
+|uart_ri_dcd_sel_i2c
 |R/W
 |Operating mode selection for pin UART_RI/DCD (determined together with bit19)

@@ -114,7 +114,7 @@ x1b: working in UART mode (decided by bit[31:28] whether to work in full functio
 10b: working in I2C mode

 |22
-|uart_txd_rxd_sel_u art	
+|uart_txd_rxd_sel_u art
 |R/W
 |Operating mode selection for pin UART_TXD/RXD

@@ -123,7 +123,7 @@ x1b: working in UART mode (decided by bit[31:28] whether to work in full functio
 `1`: working in UART mode (the bit[31:28] determines whether to work in full function mode)

 |21
-|uart_rts_cts_sel_ua rt	
+|uart_rts_cts_sel_ua rt
 |R/W
 |Operating mode selection for pin UART_RTS/CTS

@@ -131,8 +131,8 @@ x1b: working in UART mode (decided by bit[31:28] whether to work in full functio

 `1`: working in UART mode (determined by bit[31:28] whether to work in full function mode)

-|20	
-|uart_dtr_dsr_sel_u art	
+|20
+|uart_dtr_dsr_sel_u art
 |R/W
 |Operating mode selection for pin UART_DTR/DSR (determined together with bit24)

@@ -144,8 +144,8 @@ x1b: working in UART mode (decided by bit[31:28] whether to work in full functio

 10b: working in I2C mode

-|19	
-|uart_ri_dcd_sel_uar t	
+|19
+|uart_ri_dcd_sel_uar t
 |R/W
 |Operating mode selection for pin UART_RI/DCD (determined together with bit23)

@@ -157,8 +157,8 @@ x1b: working in UART mode (decided by bit[31:28] whether to work in full functio

 10b: working in I2C mode

-|18	
-|usb_oc2_sel	
+|18
+|usb_oc2_sel
 |R/W
 |Operating mode selection for pin `USB_OC2`

@@ -166,8 +166,8 @@ x1b: working in UART mode (decided by bit[31:28] whether to work in full functio

 `1`: Working in `USB_OC` mode

-|17	
-|usb_oc1_sel	
+|17
+|usb_oc1_sel
 |R/W
 |Operating mode selection for pin USB_OC1

@@ -175,8 +175,8 @@ x1b: working in UART mode (decided by bit[31:28] whether to work in full functio

 `1`: Working in `USB_OC` mode

-|16	
-|usb_oc0_sel	
+|16
+|usb_oc0_sel
 |R/W
 |Operating mode selection for pin USB_OC0

@@ -184,8 +184,8 @@ x1b: working in UART mode (decided by bit[31:28] whether to work in full functio

 `1`: working in `USB_OC` mode

-|15	
-|sata2_ledn_sel	
+|15
+|sata2_ledn_sel
 |R/W
 |Operating mode selection for pin SATA2_LEDn

@@ -193,8 +193,8 @@ x1b: working in UART mode (decided by bit[31:28] whether to work in full functio

 `1`: Operates in `SATA` mode

-|14	
-|sata1_ledn_sel	
+|14
+|sata1_ledn_sel
 |R/W
 |Operating mode selection for pin `SATA1_LEDn`

@@ -202,8 +202,8 @@ x1b: working in UART mode (decided by bit[31:28] whether to work in full functio

 `1`: Operates in `SATA` mode

-|13	
-|sata0_ledn_sel	
+|13
+|sata0_ledn_sel
 |R/W
 |Operating mode selection for pin `SATA0_LEDn`

@@ -211,8 +211,8 @@ x1b: working in UART mode (decided by bit[31:28] whether to work in full functio

 `1`: Operates in `SATA` mode

-|12:11	
-|hda_ac97_sel	
+|12:11
+|hda_ac97_sel
 |R/W
 |Operating mode selection for `HDA` pins. For the pins

@@ -226,8 +226,8 @@ For pins `HDA_SDI1/HDA_SDI2`, the operating mode is determined by bit[`11`]: `0`

 `1`: `HDA` mode

-|10	
-|spi_sel	
+|10
+|spi_sel
 |R/W
 |Operating mode selection for pin `SPI_SCK/SDI/SDO`

@@ -235,8 +235,8 @@ For pins `HDA_SDI1/HDA_SDI2`, the operating mode is determined by bit[`11`]: `0`

 `1`: Operates in `SPI` mode

-|9:8	
-|spi_csn_23_sel_spi	
+|9:8
+|spi_csn_23_sel_spi
 |R/W
 |Operating mode selection for pin `SPI_CSn2/3 00b`: operates in GPIOmode

@@ -244,8 +244,8 @@ For pins `HDA_SDI1/HDA_SDI2`, the operating mode is determined by bit[`11`]: `0`

 `10b`: Operating in `I2C` mode

-|7:6	
-|spi_csn_01_sel_spi	
+|7:6
+|spi_csn_01_sel_spi
 |R/W
 |Operating mode selection for pin `SPI_CSn0/1` 00b: Operates in GPIO mode

@@ -253,8 +253,8 @@ For pins `HDA_SDI1/HDA_SDI2`, the operating mode is determined by bit[`11`]: `0`

 `10b`: Operating in `I2C` mode

-|5	
-|i2c1_sel	
+|5
+|i2c1_sel
 |R/W
 |Operating mode selection for pin `I2C1_SCL/SDA`

@@ -262,8 +262,8 @@ For pins `HDA_SDI1/HDA_SDI2`, the operating mode is determined by bit[`11`]: `0`

 `1`: Working in I2C mode

-|4	
-|i2c0_sel	
+|4
+|i2c0_sel
 |R/W
 |Operating mode selection for pin `I2C0_SCL/SDA`

@@ -271,8 +271,8 @@ For pins `HDA_SDI1/HDA_SDI2`, the operating mode is determined by bit[`11`]: `0`

 `1`: Working in `I2C` mode

-|3	
-|pwm3_sel	
+|3
+|pwm3_sel
 |R/W
 |Operating mode selection for pin `PWM3`

@@ -280,8 +280,8 @@ For pins `HDA_SDI1/HDA_SDI2`, the operating mode is determined by bit[`11`]: `0`

 `1`: Operates in `PWM` mode

-|2	
-|pwm2_sel	
+|2
+|pwm2_sel
 |R/W
 |Operating mode selection for pin `PWM2`

@@ -289,8 +289,8 @@ For pins `HDA_SDI1/HDA_SDI2`, the operating mode is determined by bit[`11`]: `0`

 `1`: Operates in `PWM` mode

-|1	
-|pwm1_sel	
+|1
+|pwm1_sel
 |R/W
 |Operating Mode Selection for Pin `PWM1`

@@ -298,8 +298,8 @@ For pins `HDA_SDI1/HDA_SDI2`, the operating mode is determined by bit[`11`]: `0`

 `1`: Operates in `PWM` mode

-|0	
-|pwm0_sel	
+|0
+|pwm0_sel
 |R/W
 |Operating mode selection for pin `PWM0`

@@ -76,7 +76,7 @@ d|Read/Write
 |0 - Read and write to this set of registers will trigger PHY configuration access operation

 1 - Read or write to this set of registers does not trigger PHY configuration access operation, only a simple register read or write
- 
+
 |0
 |phy_cfg_R/W
 |R/W
@@ -1,7 +1,7 @@
 [[section-pcie-f1-phy-access-configuration-register]]
 === `PCIE_F1 PHY` Access Configuration Register

-This group of registers is used to control the configuration access operation that generates the PCIE_F1 PHY internal control register. 
+This group of registers is used to control the configuration access operation that generates the PCIE_F1 PHY internal control register.
 This register controls the 4 data links of PCIE_F1.

 Address Offset: `05B0`-`05B3h`
@@ -1,7 +1,7 @@
 [[section-pcie-g0-phy-hi-access-configuration-register]]
 === `PCIE_G0 PHY HI` Access Configuration Register

-This group of registers is used to control the configuration access operation that generates the PCIE_G0 PHY HI internal control register. 
+This group of registers is used to control the configuration access operation that generates the PCIE_G0 PHY HI internal control register.
 This register controls the the high 4 data links (lane4-7) of PCIE_G0.

 Address Offset: `05F8`-`05FBh`
@@ -20,7 +20,7 @@ d|Bit Field
 d|Name
 d|Read/Write
 |Description
- 
+
 |31:16
 |phy_cfg_data
 |R/W
@@ -1,7 +1,7 @@
 [[section-pcie-g0-phy-lo-access-configuration-register]]
 === `PCIE_G0 PHY LO` Access Configuration Register

-This group of registers is used to control the configuration access operation that generates the PCIE_G0 PHY LO internal control register. 
+This group of registers is used to control the configuration access operation that generates the PCIE_G0 PHY LO internal control register.
 This register controls the the lower 4 data links (lane0-3) of PCIE_G0.

 Address Offset: `05F0`-`05F3h`
@@ -1,7 +1,7 @@
 [[section-pcie-g1-phy-hi-access-configuration-register]]
 === `PCIE_G1 PHY HI` Access Configuration Register

-This group of registers is used to control the configuration access operation that generates the PCIE_G1 PHY HI internal control register. 
+This group of registers is used to control the configuration access operation that generates the PCIE_G1 PHY HI internal control register.
 This register controls the high 4 data links (lane4-7) of PCIE_G1.

 Address Offset: `0618`-`061Bh`
@@ -1,7 +1,7 @@
 [[section-pcie-g1-phy-lo-access-configuration-register]]
 === `PCIE_G1 PHY LO` Access Configuration Register

-This group of registers is used to control the configuration access operation that generates the PCIE_G1 PHY LO internal control register. 
+This group of registers is used to control the configuration access operation that generates the PCIE_G1 PHY LO internal control register.
 This register controls the the lower 4 data links (lane0-3) of PCIE_G1.

 Address Offset: `0610`-`0613h`
@@ -29,8 +29,8 @@ d|Read/Write

 `1`: The operating mode is determined by the software configuration (bit26)

-|26	
-|cfg_x4_mode	
+|26
+|cfg_x4_mode
 |R/W
 |Software configuration of `PCIE_H` operating modes

@@ -2,7 +2,7 @@
 === `PCIE_H PHY HI` Access Configuration Register

 This group of registers is used to control the configuration access operation that generates the PCIE_H PHY HI internal control register.
- This register controls the the high 4 data links (lane4-7) of PCIE_H.
+This register controls the the high 4 data links (lane4-7) of PCIE_H.

 Address Offset: `05D8`-`05DBh`

@@ -75,7 +75,7 @@ d|Read/Write
 |0 - Read or write to this group of registers will trigger the PHY configuration access operation

 1 - Read or write to this set of registers does not trigger PHY configuration access operation, only a simple register read or write
- 
+


 |0
@@ -1,7 +1,7 @@
 [[section-pcie-h-phy-lo-access-configuration-register]]
 === `PCIE_H PHY LO` Access Configuration Register

-This group of registers is used to control the configuration access operation that generates the PCIE_H PHY LO internal control register. 
+This group of registers is used to control the configuration access operation that generates the PCIE_H PHY LO internal control register.
 This register controls the the lower 4 data links (lane0-3) of PCIE_H.

 Address Offset: `05D0`-`05D3h`
@@ -67,7 +67,7 @@ d|Read/Write
 |2
 |phy_cfg_done
 |R/W
-|The completion of one access to PHY indicates the completion of reading and writing to PHY. 
+|The completion of one access to PHY indicates the completion of reading and writing to PHY.
 Write completion indicates that the written data has been written to the PHY internal register, and read completion indicates that the read data has been returned to the phy_cfg_data register

 |1
@@ -20,7 +20,7 @@ d|Bit Field
 d|Name
 d|Read/Write
 |Description
- 
+
 |31:30
 |Reserved
 |R/W
@@ -3,7 +3,7 @@

 Please refer to Section 2.5 PLL Configuration Method for the specific usage of PLL.
 This register is used to set PLL2, where output clock 2 is used to generate the CLKOUTFLEX clock, output clock 1 is used to generate the internal bus clock, and output clock 0 is used to generate the 24MHz bitclk clock required by the HDA.
- 
+
 Output Clock 1 is used to generate the internal bus clock, and Output Clock 0 is used to generate the 24MHz bitclk clock required by the HDA.

 Address Offset: `04A0`-`04A3h`
@@ -1,8 +1,7 @@
 [[hpet-controller]]
 == HPET Controller

-The HPET controller is compatible with standard specifications. Internally, it includes a 64-bit main counter and three 32-bit timers (comparators). Of the three timers, 
-timer 0 supports both periodic-capable and non-periodic interrupts, while timers 1 and 2 support only non-periodic interrupts. 
+The HPET controller is compatible with standard specifications. Internally, it includes a 64-bit main counter and three 32-bit timers (comparators). Of the three timers, timer 0 supports both periodic-capable and non-periodic interrupts, while timers 1 and 2 support only non-periodic interrupts.

 include::hpet-controller/access-address.adoc[]

@@ -96,7 +96,7 @@ Default value: `1312D00h` (`20ns` clock period).
 |COUNT_SIZE_CAP
 |The width of the master timer. This chip is a `64`-bit master timer. Value: `1b`.

-`0`: `32` bits 
+`0`: `32` bits

 `1`: `64` bits
 |RO
@@ -280,7 +280,7 @@ The software can directly modify the accumulator for the periodic period by writ

 `0`: the timer is not capable of generating periodic interrupts.
 |RO
- 
+
 |3
 |T0_TYPE_CNF
 |Timer 0 cycle interrupt configuration.
@@ -378,12 +378,13 @@ Timer 1 comparator value. Same as Timer 0.
 Address Offset: `140`-`147h`

 Attribute: RO, R/W
- 
+
 Default value: `00h`

-Size:`8`
+Size: `8`

-Timer 2 configuration and function registers. Same as Timer 0.
+Timer 2 configuration and function registers.
+Same as Timer 0.

 *Timer 2 Comparator Value Register*

@@ -395,4 +396,4 @@ Default value: `FFFFFFFFh`

 Size:`8`

-Timer 2 comparator value. Same as Timer 0. 
+Timer 2 comparator value. Same as Timer 0.
@@ -1,7 +1,7 @@
 [[ht-controller]]
 == HT Controller

-The bridge HT interface supports a maximum bi-directional 16-bit data width and an operating frequency of 2.0 GHz. 
+The bridge HT interface supports a maximum bi-directional 16-bit data width and an operating frequency of 2.0 GHz.
 After the connection is established by automatic system initialization, the user can change the width and operating frequency and re-initialize by modifying the corresponding configuration registers in the protocol.

 The main features of the bridge HT interface are as follows:
@@ -210,7 +210,7 @@ Attribute: R/W, RO

 Default value: `0000h`

-Size: `16` bit
+Size: `16` bits

 [[bctrl-ht-bridge-control-register]]
 .BCTRL-HT bridge control register
@@ -249,7 +249,7 @@ Attribute: R/W, RO

 Default value: `0000h`

-Size: `16` bit
+Size: `16` bits

 [[didcmd-device-id-command-register]]
 .DIDCMD-device ID command register
@@ -286,10 +286,10 @@ Size: `16` bit
 Address Offset: `44`-`45h`

 Attribute: R/W, RO
- 
+
 Default value: `2000h`

-Size: `16` bit
+Size: `16` bits

 [[lksc0-link-status-control-register-0]]
 .LKSC0-Link status control register 0
@@ -471,7 +471,7 @@ Attribute: R/W, RO
 Default value: `0060h`

 Size: `32` bits
- 
+
 [[lkfreqcfg0-link-frequency-configuration-register-1]]
 .LKFREQCFG0-Link frequency configuration register 1
 [%header,cols="1m,^2m,^1,4"]
@@ -953,7 +953,7 @@ Accesses hit by the P2P receive window are sent directly back to the HT bus as P
 When the window is enabled, the address window hit condition is: ( ADDR & WIN_MASK ) == ( WIN_BASE & WIN_MASK ). Note: ADDR here refers to the high 16 bits of the address (bit[39:24], the address sent to the HT bus is only 40 bits).

 For example, 1111111100000000b,1100000000000000b are legal configurations, while 1011111100000000b,11010000000000b are not.
-The number of zeros in MASK indicates the size of the address window. 
+The number of zeros in MASK indicates the size of the address window.

 *RXP2PWIN0-P2P receive window 0*

@@ -3,27 +3,23 @@

 ==== HT Working Mode

-When chip pin HT_8x2 is configured to 0, the bridge operates in single mode, where only one processor is directly connected to the bridge via the HT bus, 
-and only one HT controller (HT lo) is operating inside the bridge, while the other HT controller (HT hi) is not available.
+When chip pin HT_8x2 is configured to 0, the bridge operates in single mode, where only one processor is directly connected to the bridge via the HT bus, and only one HT controller (HT lo) is operating inside the bridge, while the other HT controller (HT hi) is not available.

-The HT link can operate in either 8-bit or 16-bit mode, and the software can configure the data width used (the maximum available width also depends on the PCB hardware connection), 
-when the data link is controlled by controller lo. The data link is controlled by the controller lo.
+The HT link can operate in either 8-bit or 16-bit mode, and the software can configure the data width used (the maximum available width also depends on the PCB hardware connection), when the data link is controlled by controller lo. The data link is controlled by the controller lo.

-When the chip pin HT_8x2 is configured to 1, the bridge operates in dual mode, where two processors can be connected directly to the bridge via the HT bus, and the two HT controllers inside the bridge are operating simultaneously,
- controlling the low 8 bits and high 8 bits of the data link respectively. Software can control both HT controllers via the HT bus of both processors. When operating in dual mode, 
- the software needs to configure the HT DMA routing configuration (see section 4.1 HT Clock Enable and DMA Routing Configuration) to send DMA accesses to the corresponding HT controller.
+When the chip pin HT_8x2 is configured to 1, the bridge operates in dual mode, where two processors can be connected directly to the bridge via the HT bus, and the two HT controllers inside the bridge are operating simultaneously, controlling the low 8 bits and high 8 bits of the data link respectively. Software can control both HT controllers via the HT bus of both processors. When operating in dual mode, the software needs to configure the HT DMA routing configuration (see section 4.1 HT Clock Enable and DMA Routing Configuration) to send DMA accesses to the corresponding HT controller.

 ==== HT Address Space

 The address space for processor accesses is described in Section 3.

-The HT module has several internal address windows for configuring CPU accesses and DMA accesses. For CPU accesses, the bridge chip acts as the accessee and the corresponding configuration window is called the receive window; 
+The HT module has several internal address windows for configuring CPU accesses and DMA accesses. For CPU accesses, the bridge chip acts as the accessee and the corresponding configuration window is called the receive window;
 for DMA accesses, the bridge chip acts as the access initiator and the corresponding window is called the send window.

-The receive window consists of two types: the P2P access window and the normal access window. Accesses that fall within the P2P access window are forwarded directly back to the HT bus as P2P commands and are not sent to the internal devices of the bridge chip; 
+The receive window consists of two types: the P2P access window and the normal access window. Accesses that fall within the P2P access window are forwarded directly back to the HT bus as P2P commands and are not sent to the internal devices of the bridge chip;
 accesses that fall within the normal access window are sent to the internal devices of the bridge chip as accesses to the internal devices of the bridge chip. The P2P access window has a higher priority than the normal access window.
- Accesses that do not hit in either of the two types of receive windows are forwarded directly back to the HT bus as P2P commands.
+Accesses that do not hit in either of the two types of receive windows are forwarded directly back to the HT bus as P2P commands.

 DMA accesses are sent out through the HT's non-Post channel by default, and the Post send window is set internally in the bridge to send DMA accesses out through the HT's Post channel.
- That is, DMA accesses that hit in the Post send window are sent to the HT bus via the HT's Post channel, and DMA accesses that do not hit in the Post send window are sent to the HT bus via the HT's non-Post channel. 
- In general, the Post send window should not be enabled and all DMA accesses should be sent out through the HT's non-Post channel.
+That is, DMA accesses that hit in the Post send window are sent to the HT bus via the HT's Post channel, and DMA accesses that do not hit in the Post send window are sent to the HT bus via the HT's non-Post channel.
+In general, the Post send window should not be enabled and all DMA accesses should be sent out through the HT's non-Post channel.
@@ -1,7 +1,7 @@
 [[interrupt-controller]]
 == Interrupt Controller

-The bridge chip has an integrated advanced programmable interrupt controller. 
+The bridge chip has an integrated advanced programmable interrupt controller.
 The internal interrupt controller supports up to `64` interrupt sources and two interrupt outputs.

 The bridge supports interrupt transmission via both interrupt lines and HT messages.
@@ -12,16 +12,16 @@ In the HT message method, no additional interrupt pin connection is required, an

 The bridge chip supports the use of only one of these two interrupt methods and is valid for all `64` interrupt sources simultaneously.

-The bridge supports outputting dual interrupts, meaning that interrupt information can be routed to both processors. 
+The bridge supports outputting dual interrupts, meaning that interrupt information can be routed to both processors.
 The correspondence between interrupt sources and interrupt outputs is configurable, and this configuration is valid for both interrupt line and HT message packet interrupt modes.

-In interrupt line interrupt mode, the interrupt lines of all interrupt-capable devices inside the bridge chip are sent directly to the bridge chip's interrupt controller, and external PCIE devices send interrupts to the bridge chip's internal PCIE controller via legacy interrupts. 
+In interrupt line interrupt mode, the interrupt lines of all interrupt-capable devices inside the bridge chip are sent directly to the bridge chip's interrupt controller, and external PCIE devices send interrupts to the bridge chip's internal PCIE controller via legacy interrupts.
 The bridge's interrupt controller finally interrupts the processor via the bridge's interrupt pin signal.

 In HT message interrupt mode, all devices inside the bridge except the PCIE send interrupt information to the interrupt controller of the bridge via the interrupt line, and the interrupt controller converts the interrupt information into HT message packets and sends them to the processor via the HT bus.

-For PCIE devices, there are two interrupt modes, one is that the device still uses legacy interrupt and sends the interrupt information to the interrupt controller of the bridge through the interrupt line of the PCIE controller of the bridge, and the interrupt controller is responsible for converting the interrupt information into HT message packets; 
-the other is to enable the `MSI` interrupt function of the PCIE device, and the `MSI` interrupt message of the device passes through the PCIE controller of the bridge. 
+For PCIE devices, there are two interrupt modes, one is that the device still uses legacy interrupt and sends the interrupt information to the interrupt controller of the bridge through the interrupt line of the PCIE controller of the bridge, and the interrupt controller is responsible for converting the interrupt information into HT message packets;
+the other is to enable the `MSI` interrupt function of the PCIE device, and the `MSI` interrupt message of the device passes through the PCIE controller of the bridge.
 The other is to enable the `MSI` interrupt function of the PCIE device, and the device's `MSI` interrupt messages are converted into HT packets by the conversion module inside the bridge's PCIE controller.

 Note that in the latter mode, the interrupt packets of the PCIE device do not support interrupt routing and can only be sent to the HT lo controller of the bridge.
@@ -34,7 +34,7 @@ The figure above illustrates the hardware modules and processes involved in inte

 The figure shows the process of the two interrupt methods, the upper part shows the interrupt through the interrupt line INTn0, and the lower part shows the interrupt through the HT message packet.

-The interrupt intX from the device (except for PCIE devices operating in `MSI` mode) is sent to the 7A internal interrupt controller, where it is routed to the bridge pin or converted into an HT packet and sent to the 3A's HT controller, which receives the interrupt through the external interrupt pin or HT controller interrupt, 
+The interrupt intX from the device (except for PCIE devices operating in `MSI` mode) is sent to the 7A internal interrupt controller, where it is routed to the bridge pin or converted into an HT packet and sent to the 3A's HT controller, which receives the interrupt through the external interrupt pin or HT controller interrupt,
 and is routed through the interrupt to The interrupt controller of 3A receives the interrupt through external interrupt pin or HT controller interrupt and interrupts a processor core through interrupt route.

 The address space of the bridge interrupt controller is 4KB, and the starting address (internal space of the bridge) is configured by the BIOS.
@@ -421,11 +421,11 @@ Size: `32` bits

 *HT interrupt message packet enable register*

-Address Offset: `040`-`043h` 
+Address Offset: `040`-`043h`

 Default value: `00000000h`

-Attribute: R/W 
+Attribute: R/W

 Size: `32` bits

@@ -614,11 +614,11 @@ Size: `32` bits

 *INT_AUTO_CTRL1 register*

-Address Offset: `0E0`-`0E3h` 
+Address Offset: `0E0`-`0E3h`

 Default value: `00000000h`

-Attribute: R/W 
+Attribute: R/W

 Size: `32` bits

@@ -734,7 +734,7 @@ Size: `32` bits
 |i2c_int_route
 |R/W
 |`I2C` Interrupt Routing Configuration Register
- 
+
 |1:0
 |uart_int_route
 |R/W
@@ -1607,7 +1607,7 @@ Size: `32` bits
 |Name
 |Read/Write
 |Description
- 
+
 |31:24
 |acpi_int_route
 |R/W
@@ -2018,6 +2018,6 @@ Size: `32` bits
 |31:0
 |int_polarity
 |R/W
-|High `32` bits of the interrupt level trigger 
+|High `32` bits of the interrupt level trigger
 polarity register (bit`[63:32]`)
 |===
@@ -2,8 +2,7 @@
 === Detailed Description of Interrupt Handling Process

 In the interrupt line interrupt mode, the interrupt controller of the bridge chip receives the device interrupt and sets the corresponding interrupt output pin low according to the interrupt routing configuration.
-The processor receives the interrupt through the interrupt input pin, 
-and the processor obtains the current interrupt source routed to itself by reading the corresponding ISR (interrupt in service register) register within the bridge chip interrupt controller.
+The processor receives the interrupt through the interrupt input pin, and the processor obtains the current interrupt source routed to itself by reading the corresponding ISR (interrupt in service register) register within the bridge chip interrupt controller.
 The interrupt processing process is:

 . The interrupt controller of the bridge receives the device interrupt; (hardware)
@@ -3,8 +3,8 @@

 For the bridge chip, AC97 DMA interrupts are edge triggered, gpio interrupts can be configured to be level triggered or edge triggered as needed, and the rest of the interrupts are level triggered and active high.

-For PCIE devices, one way is to use the interrupt line of the PCIE controller inside the bridge to transmit the interrupt; 
+For PCIE devices, one way is to use the interrupt line of the PCIE controller inside the bridge to transmit the interrupt;
 the other way is to use the MSI interrupt of the PCIE device directly.

-In the PCIE MSI interrupt method, when the PCIE controller inside the bridge receives an MSI interrupt, it converts it directly into an HT interrupt message packet to send to the HT controller. 
-Therefore, the software needs to be careful to distinguish the MSI interrupt vector of the PCIE device from the HT interrupt vector configured by the internal device of the bridge. 
+In the PCIE MSI interrupt method, when the PCIE controller inside the bridge receives an MSI interrupt, it converts it directly into an HT interrupt message packet to send to the HT controller.
+Therefore, the software needs to be careful to distinguish the MSI interrupt vector of the PCIE device from the HT interrupt vector configured by the internal device of the bridge.
@@ -1,13 +1,13 @@
 [[interrupt-distribution-modes]]
 === Interrupt Distribution Modes

-The bridge supports dual interrupt outputs, so that different interrupt sources or multiple interrupts from the same interrupt source can be distributed between the two interrupt outputs. 
+The bridge supports dual interrupt outputs, so that different interrupt sources or multiple interrupts from the same interrupt source can be distributed between the two interrupt outputs.
 The bridge chip supports interrupt hardware load balancing, which allows interrupts to be distributed between the two outputs preset by software in four modes.:

-. Fixed distribution mode - Distribution is done according to the routing method configured in the interrupt routing configuration register. 
+. Fixed distribution mode - Distribution is done according to the routing method configured in the interrupt routing configuration register.
 In this mode, the routing configuration register must be one-hot encoded, meaning that an interrupt can only be routed to one interrupt output.

-. Rotating distribution mode - In this mode, each new interrupt generated is routed to the next valid interrupt output according to the route vector configuration in the Route_Entry register. 
+. Rotating distribution mode - In this mode, each new interrupt generated is routed to the next valid interrupt output according to the route vector configuration in the Route_Entry register.
 The route to the next valid interrupt output is configured in the Route_Entry register.

 . Idle distribution mode - jumps to an idle interrupt output.
@@ -15,5 +15,5 @@ In this mode, when each new interrupt is generated, it first detects if there is
 if there is already an unprocessed interrupt on the next interrupt output, it continues to detect the next processor core.

 . Busy distribution mode - the current interrupt output is busy then jumps to its left (0->1->2->3) candidate interrupt output.
-When each new interrupt is generated in this mode, it first detects whether there is already an unprocessed interrupt on the interrupt output of the last interrupt, and if not, continues to interrupt that interrupt output, and if there is an unprocessed interrupt, it is routed to the next interrupt output as configured in the Entry register. 
+When each new interrupt is generated in this mode, it first detects whether there is already an unprocessed interrupt on the interrupt output of the last interrupt, and if not, continues to interrupt that interrupt output, and if there is an unprocessed interrupt, it is routed to the next interrupt output as configured in the Entry register.
 It should be noted that once AUTO_CTRL0/1 has been configured, it should not be modified in the middle of the run. It is recommended that the software use fixed distribution mode.
@@ -1,8 +1,7 @@
 [[interrupt-source-assignment]]
 === Interrupt Source Assignment

-The internal devices of the bridge chip are connected to the interrupt controller via interrupt lines. The interrupt pin assignment of the interrupt controller is shown in the follow Table. AC97 controller and HDA controller share one interrupt pin, `GPIO0-3` share one interrupt pin, and other `GPIOs` share one interrupt pin. 
-
+The internal devices of the bridge chip are connected to the interrupt controller via interrupt lines. The interrupt pin assignment of the interrupt controller is shown in the follow Table. AC97 controller and HDA controller share one interrupt pin, `GPIO0-3` share one interrupt pin, and other `GPIOs` share one interrupt pin.

 [[bridge-chip-interrupt-controller-interrupt-source-assignment]]
 .Bridge chip interrupt controller interrupt source assignment
@@ -1,8 +1,8 @@
 [[address-space-division]]
 === Address Space Division

-The PCIE controller in the bridge has a standard PCIE configuration header, so the internal registers of the PCIE controller and the address space of its downstream devices are managed by the information in its configuration header. 
-The address-related registers in the configuration header are determined during the PCI device scan. 
+The PCIE controller in the bridge has a standard PCIE configuration header, so the internal registers of the PCIE controller and the address space of its downstream devices are managed by the information in its configuration header.
+The address-related registers in the configuration header are determined during the PCI device scan.

 Because the bridge's PCIE controller can only operate in RC mode, its configuration header is of type TYPE1.

@@ -634,7 +634,7 @@ m|
 |3
 4+<|*`CTW_EN` - R/W*

-Enable THERMAL WARNING interrupt.	
+Enable THERMAL WARNING interrupt.
 m|

 m|2
@@ -654,7 +654,7 @@ m|0

 This bit sets the polarity of the `LID`.
 m|
-|===	
+|===

 *`RST_CNT`: Reset Control Register*

@@ -1,12 +1,12 @@
 [[uart-controller]]
 == UART Controller

-The integrated UART controller of the bridge chip complies with the RS232 standard and the controller is designed to be compatible with the 16550A. 
+The integrated UART controller of the bridge chip complies with the RS232 standard and the controller is designed to be compatible with the 16550A.
 The internal clock frequency of the UART controller is 50 MHz and the maximum baud rate supported by the UART bus is 460800.

 The bridge chip integrates four UART controllers, which are arranged in the UART module.
- In addition, UART1, UART2 and UART3 can only work in two-wire UART mode, and UART0 can work in full-function UART mode or two-wire UART mode. 
-In addition, UART can be multiplexed as GPIO function and some UART pins can be multiplexed as I2C function. 
+In addition, UART1, UART2 and UART3 can only work in two-wire UART mode, and UART0 can work in full-function UART mode or two-wire UART mode.
+In addition, UART can be multiplexed as GPIO function and some UART pins can be multiplexed as I2C function.
 The pin multiplexing configuration registers related to UART are described in Section 4.4.

 [[uart-function-reuse]]
@@ -10,7 +10,7 @@ The 4 UART controllers are distinguished by bit `[9:8]`, and the internal physic
 [%header,cols="3*^1m"]
 |===
 |Address bit
-|Composition 
+|Composition
 |Remarks

 |[15:10]
@@ -86,7 +86,7 @@ Reset value: `0x00`

 `1`: Open
 |===
- 
+
 *Interrupt identification register (IIR)*

 Offset: `0x02`
@@ -471,8 +471,6 @@ FIFO is cleared when writing data to the FIFO.
 `0`: No overflow.

 `1`: There is data overflow.
- 
-

 |0
 |DR
@@ -65,7 +65,9 @@ git clone https://github.com/loongson/LoongArch-Documentation
 +
 [source]
 ----
-cd LoongArch-Documentation && bundle config set --local path .bundle/gems && bundle
+cd LoongArch-Documentation
+bundle config set --local path .bundle/gems
+bundle
 ----

 . 现在您可以生产文档了。
@@ -147,6 +149,7 @@ Asciidoctor PDF 从 AsciiDoc 生成的 PDF 的样式见 https://github.com/ascii
 . https://docs.microsoft.com/zh-cn/windows/win32/fileio/maximum-file-path-limitation?tabs=cmd#enable-long-paths-in-windows-10-version-1607-and-later[启用] 长路径支持。

 . 使用最新的 https://git-scm.com/downloads[Git] 。
+用 Git Bash 执行所有命令。
 运行 `git config --global core.longpaths true` 来修改全局配置或在仓库中运行 `git config core.longpaths true` 来修改本地配置。

 . 使用最新的 https://www.jruby.org/download[JRuby] 来替代 Ruby。
@@ -33,7 +33,7 @@ To make it easier to download, each HTML page contains embedded CSS and images.
 ** link:LoongArch-Vol3-EN.pdf[PDF version].
 ** https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol3-v1.00-CN.pdf[Original document].

-* Loongson 3A5000/3B5000 Registers Technical Reference Manual - Multicore Processor Architecture, Register Descriptions and System Software Programming Guide: This manual introduces the Loongson 3A5000/3B5000 multicore processor architecture and register descriptions.
+* Loongson 3A5000/3B5000 Processor Reference Manual - Multicore Processor Architecture, Register Descriptions and System Software Programming Guide: This manual introduces the Loongson 3A5000/3B5000 multicore processor architecture and register descriptions.
 ** link:Loongson-3A5000-usermanual-EN.html[HTML version].
 ** link:Loongson-3A5000-usermanual-EN.pdf[PDF version].
 ** https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-v1.02-CN.pdf[Original document].
@@ -78,7 +78,9 @@ git clone https://github.com/loongson/LoongArch-Documentation
 +
 [source]
 ----
-cd LoongArch-Documentation && bundle config set --local path .bundle/gems && bundle
+cd LoongArch-Documentation
+bundle config set --local path .bundle/gems
+bundle
 ----

 . Now you can generate the documents.
@@ -158,6 +160,7 @@ If you are using an earlier version, or if you don`'t want to do some extra oper
 . https://docs.microsoft.com/en-us/windows/win32/fileio/maximum-file-path-limitation#enable-long-paths-in-windows-10-version-1607-and-later[Enable] long paths.

 . Use the latest https://git-scm.com/downloads[Git].
+Execute all commands with Git Bash.
 Run `git config --global core.longpaths true` to modify the global configuration or run `git config core.longpaths true` in the repo to modify the local configuration.

 . Use the latest https://www.jruby.org/download[JRuby] instead of Ruby.