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Sometimes (especially with big images) reading pitch 0 from card's register
returns 0 (probably due to full card's FIFO), which leads to SIGFPE later. Fixed (or workarounded) by rereading pitch0, until it's not zero. git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@10971 b3059339-0415-0410-9bf9-f77b7e298cf2
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@@ -419,6 +419,7 @@ void rivatv_overlay_start (struct rivatv_info *info,int bufno){
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/*update depth & dimensions here because it may change with vo vesa or vo fbdev*/
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info->chip.lock (&info->chip, 0);
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do {
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switch (info->chip.arch) {
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case NV_ARCH_03:
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pitch0 = info->chip.PGRAPH[0x00000650/4];
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@@ -430,6 +431,9 @@ void rivatv_overlay_start (struct rivatv_info *info,int bufno){
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pitch0 = info->chip.PGRAPH[0x00000670/4];
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break;
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}
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if (pitch0 == 0)
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printf("[nvidia_vid]: pitch0 = 0!!! Rereading\n");
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} while (pitch0 == 0);
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VID_WR08(info->chip.PCIO, 0x03D4, 0x28);
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bpp = VID_RD08(info->chip.PCIO,0x03D5);
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if(bpp==3)bpp = 4; //fixme do nvidia cards support 24bpp?
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@@ -438,7 +442,7 @@ void rivatv_overlay_start (struct rivatv_info *info,int bufno){
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if(!bpp)printf("[nvidia_vid] error invalid bpp\n");
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else
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{
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// printf("[nvidia_vid] video mode: %ux%u@%u\n",screen_x = pitch0/bpp,(pitch0/bpp*3)/4,info->depth);
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// printf("[nvidia_vid] video mode: %ux%u@%u\n",info->screen_x = pitch0/bpp,(pitch0/bpp*3)/4,info->depth);
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info->screen_x = pitch0/bpp;
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}
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@@ -673,6 +677,7 @@ int vixInit(void){
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{
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uint32_t bpp=0,pitch0=0;
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info->chip.lock (&info->chip, 0);
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do {
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switch (info->chip.arch) {
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case NV_ARCH_03:
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pitch0 = info->chip.PGRAPH[0x00000650/4];
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@@ -684,6 +689,9 @@ int vixInit(void){
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pitch0 = info->chip.PGRAPH[0x00000670/4];
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break;
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}
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if (pitch0 == 0)
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printf("[nvidia_vid]: pitch0 = 0!!! Rereading\n");
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} while (pitch0 == 0);
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VID_WR08(info->chip.PCIO, 0x03D4, 0x28);
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bpp = VID_RD08(info->chip.PCIO,0x03D5);
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if(bpp==3)bpp = 4; //fixme do nvidia cards support 24bpp?
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